Patent classifications
G06F7/582
Checkpointing
A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at successive points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.
Apparatus and method for unbreakable data encryption
An encryption specification named “MetaEncrypt” implemented as a method and associated apparatus is disclosed for unbreakable encryption of data, code, applications, and other information that uses a symmetric key for encryption/decryption and to configure the underlying encryption algorithms being utilized to increase the difficulty of mathematically modeling the algorithms without possession of the key. Data from the key is utilized to select several encryption algorithms utilized by MetaEncrypt and configure the algorithms during the encryption process in which block sizes are varied and the encryption technique that is applied is varied for each block. Rather than utilizing a fixed key of predetermined length, the key in MetaEncrypt can be any length so both the key length and key content are unknown. MetaEncrypt's utilization of key data makes it impossible to model its encryption methodology to thereby frustrate cryptographic cracking and force would be hackers to utilize brute force methods to try to guess or otherwise determine the key.
SYSTEM AND METHOD OF PROVIDING A FEATURE GAME WITH MULTIPLE GAME INSTANCES
A gaming machine provides a base game, from which a hold and spin feature game is triggered when a determined number of configurable symbols are displayed in a base game outcome. When the feature game is triggered, the configurable symbols are held in place on the display and the player is provided one or more spins during the feature game in which to collect additional configurable symbols. Any additional configurable symbols are retained on the display during subsequent spins until the feature game is completed. At the end of the feature game, the player is awarded a prize based on the values carried by the configurable symbols. An ante bet entitles to player to additional game instances in the hold and spin feature game. The additional game instances duplicate the configurable symbols that trigger the feature game, but are played independently from one another during the hold and spin feature.
SYSTEM FOR USER AUTHENTICATION BASED ON LINKING A RANDOMLY GENERATED NUMBER TO THE USER AND A PHYSICAL ITEM
A system for authenticating recipients of a physical item based on generating a random number and linking the random number to the physical item and the intended recipient. Once the intended recipient is in possession of the physical item and the generated random number, the intended recipient is authorized for the purpose of using/processing the physical item by presenting the random number for recipient authentication. In other specific embodiments of the invention, the physical item is generated with the random number included in place of personal information associated with the provider.
Parallelization of random number generators
System and method for pseudo-random number generation based on a recursion with significantly increased multithreaded parallelism. A single pseudo-random generator program is assigned with multiple threads to process in parallel. N state elements indexed incrementally are arranged into a matrix comprising x rows, where a respective adjacent pair of state elements in a same column are related by g=(M+j)mod N, wherein j and g represent indexes of the pair of state elements. x can be determined through an modular manipulative inverse of M and N. The matrix can be divided into sections with each section having a number of columns, and each thread is assigned with a section. In this manner, the majority of the requisite interactions among the state elements occur without expensive inter-thread communications, and further each thread may only need to communicate with a single other thread for a small number of times.
Cryptographic key generation using a stored input value and a stored count value
Embodiments of an invention for cryptographic key generation using a stored input value and a stored count value have been described. In one embodiment, a processor includes non-volatile storage storing an input value and a count value, and logic to generate a cryptographic key based on the stored input value and the stored count value.
Low-power activity monitoring
Some examples include a secure low-power sensor platform able to be used for activity monitoring or other purposes. For instance, a sensor system may sense sparse signals using compressed sensing. As one example, compressed sensing may be used to obtain sparse signals from analog sensor signals received from one or more sensors. The data obtained by compressed sensing may be sent subsequently to a computing device to reconstruct the sensor signal. Examples herein enable lower power usage, lower cost, and lower weight than conventional devices, while also enabling processing advantages, such as less overall data to process and lower data storage utilization.
METHOD OF LINEAR TRANSFORMATION (VARIANTS)
The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations which operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data.
The technical result relates to enabling to select inter-related parameters (performance and required amount of memory) for a particular computing system when implementing a high-dimensional linear transformation.
The use of the present method allows to reduce the amount of consumed memory at a given word size of processors employed.
To this end, based on a specified linear transformation, a modified linear shift register of Galois-type or Fibonacci-type is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.
Extended reality authentication
Methods and systems for secure authentication in an extended reality (XR) environment are described herein. An XR environment may be output by a computing device and for display on a device configured to be worn by a user. A first plurality of images may be determined via the XR environment. The first plurality of images may be determined based on a user looking at a plurality of objects, real or virtual, in the XR environment. The first plurality of images may be sent to a server, and the server may return a second plurality of images. A public key and private key may be determined based on different portions of each of the second plurality of images. The public key may be sent to the server to register and/or authenticate subsequent communications between the computing device and the server.
Generating and checking a quaternary pseudo random binary sequence
An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence (“QPRBS”). In an apparatus, there is a pseudo random binary sequence (“PRBS”) generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is configured to receive the mask output and the PRBS to bitwise mask the PRBS with the mask output to generate the QPRBS.