A method for performing an auction implemented via an exchange computer system includes receiving, from a user device, a security transaction order, receiving a first matching order, initiating a delay timer that runs for a first period of time, initiating an auction timer that runs for a second period of time, determining that the first period of time has expired, notifying a plurality of market participants of an auction, receiving, during the second period of time, one or more additional matching orders, wherein each of the one or more additional matching orders includes a request for participation in the auction, determining that the second period of time has expired, and facilitating a transaction based on the security transaction order.

A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.

A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.

A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.

A random number generator includes a ring oscillator, an inversion selecting circuit, and controller. The ring oscillator includes an inverter chain having at least one inverter and generates an output signal. The inversion selecting circuit controlling a phase inverter configured to invert a signal of the inverter chain. The controller is configured to operate the inversion selecting circuit to provide an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and operate the inversion selecting circuit to not provide the output of the phase inverter during a second operation mode for generating a random number.

Devices and techniques for replay protection nonce generation are described herein. A hash, of a first length, can be produced from a first input. A first subset of the hash can be extracted as a selector. A second subset of the hash can be selected using the selector. Here, the second subset has a second length that is less than the first length. The second subset can be transmitted as a nonce for a freshness value in a replay protected communication.

A clock signal generation circuit includes: a triangular wave generation circuit configured to generate a triangular wave signal; a pseudo-random number generation circuit configured to generate a pseudo-random number signal; a limiter circuit configured to perform a limitation process of limiting an amount of change per unit time in the pseudo-random number signal and generate the pseudo-random number signal subjected to the limitation process as a limiter signal; a linear arithmetic circuit configured to generate a frequency control signal by performing a linear arithmetic operation on the triangular wave signal and the limiter signal; and an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal.

An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for an autonomous pseudo-random seed generator (APRSG) for embedded computing devices, which may include IoT-type devices, such as implemented in connection with one or more computing and/or communication networks and/or protocols.

A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.