An optimization device includes: processing circuits each configured to: hold a first value of a neuron of an Ising model; and perform a process to determine whether to permit updating of the first value based on information of the Ising model and information about a target neuron; a control circuit configured to: set, while causing a portion of the processing circuits to perform the process for a partial neuron group, information to be used for the process for a first neuron other than the partial neuron group in a first processing circuit; cause a second processing circuit among the portion of the processing circuits to inactivate the process; and cause the first processing circuit to start the process for the first neuron; and an update neuron selection circuit configured to: select the target neuron from one or more update permissible neurons; and update the value of the target neuron.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

The disclosure includes: acquiring first data; grouping the first data to obtain K packet sub-data; inputting a preset primer into a random generator to obtain 4T random number sequences, 4.sup.T>K; determining the packet sub-data corresponding to the ith random number sequence, and performing exclusive or (XOR) operation on the determined packet sub-data to obtain data information DATAi, and obtaining a DNA molecular chain according to the data information DATAi, the preset primer and the generation times capacity of the random generator; performing DNA sequence synthesis on the plurality of DNA molecular chains to obtain target storage data. In the disclosure, in the process of coding the first data to obtain a DNA molecular chain, a random generator is added to greatly simplify the coding process and implement efficient and accurate coding on the first data. The disclosure may be widely applied to a field of data storage technologies.

A random number generator is implemented within a digital processor by: a) searching an internal timestamp register which counts clock pulses for sequencing the processor; b) extracting at a given time n bits from the least significant bits of the register, n>1; c) using the n bits extracted at step b) as constituent bit(s) of a N-bit random number (34) to be generated; d) reiterating steps a) to c) until obtaining the N bits of the random number; and e) providing the random number to an application circuit or software.

According to certain embodiments, a method comprises performing a posture assessment at a trust anchor in order to determine whether a hardware component is authorized to run on a product. Performing the posture assessment comprises determining a random value (K), encrypting the random value (K) using a long-term key associated with the hardware component in order to yield an encrypted value, communicating the encrypted value to the hardware component, and receiving, from the hardware component, a message encrypted using the random value (K). The message comprises an identifier associated with the hardware component. Performing the posture assessment further comprises determining whether the hardware component is authorized to run on the product based at least in part on the identifier associated with the hardware component. The method further comprises performing an action that depends on whether the hardware component is authorized to run on the product.

Methods, systems, and devices for memory operations are described. First scrambling sequences may be generated for first addresses of a memory device after an occurrence of a first event, where the first addresses may be associated with commands received at the memory device. Portions of the memory array corresponding to the first address may be accessed based on the first scrambling sequences. After an occurrence of a subsequent event, second scrambling sequences may be generated for the first addresses, where the second scrambling sequences may be different than the first set of scrambling sequences. After the occurrence of the subsequent event, the portions of the memory array may be accessed based on the second scrambling sequences.

A data collection and analysis method includes applying a first noise step to an original data stream with an original character to generate a first data stream with a first character; and applying a second noise step to the first data stream to generate a second data stream with a second character, wherein a first variation between the original character and the first character is greater than a second variation between the original character and the second character.

A semiconductor device and a method of verifying random number data capable of preventing erroneous judgement of data having periodicity as a random number and verifying randomness of random number data with high accuracy are provided. The semiconductor device includes a random number generator for generating random number data as serial data, and a health test circuit for verifying randomness of the random number data. The health test circuit handles the random number data as a data string of n-bit data by dividing the random number data by n bits (n is an integer larger than or equal to two). and verifies randomness based on the n-bit data.

Systems and methods for controlling a graphical user interface in a live-game environment are disclosed. The systems and methods comprise obtaining a signal indicative of an output of a Hardware Random Number Generator (HRNG). The output of the HRNG comprising a symbol (e.g. an integer) within a predefined set comprising a plurality M of unique symbols (e.g. 1-75). Further comprising providing a graphical user interface on a display of a remote electronic device, where the graphical user interface comprising a graphical representation having a live video stream (or video feed) of at least the output of the HRNG, and a plurality of graphical elements, each graphical element defining or embodying a virtual card. Further comprising identifying the symbol of the output of the HRNG, determining a virtual card score for each virtual card of the plurality of virtual cards based on the identified symbol, and updating the graphical representation.

An example private processing pipeline may include: a masked decryption unit to perform a masked decryption operation transforming input data into masked decrypted data; a masked functional unit to produce a masked result by performing a masked operation on the masked decrypted data; and a masked encryption unit to perform a masked encryption operation transforming the masked result into an encrypted result.