An electronic circuit and a method of making the same includes a multiplier circuit configured to perform a multiplication of a first input signal with a second input signal. The first input signal is a binary input signal that includes a sequence of input bits. The electronic circuit further includes an oscillator circuit configured to receive a result signal of the multiplication from the multiplier and to provide output pulses having an output frequency which is dependent on the result signal of the multiplication and a digital counter circuit configured to count the output pulses. The digital counter circuit is configured to provide a plurality of counter bits and to select one of the plurality of counter bits for incrementation in dependence on a significance of the corresponding input bit of the sequence of input bits.

Example implementations described herein are directed to systems and methods that include the storage of I/F communication activity during a co-execution and a repeater to reproduce such I/F communication activity. Thus in a subsequent re-execution of the simulation or applications, one or more of the simulations or applications utilized can be replaced with a repeater without requiring the full execution of the simulation or application, thereby saving license usage as well as requiring fewer hardware resources for execution.

A system for evaluating a multiply and add expression. The system comprises an encoder for encoding variables of the multiply and add expression on a time domain signal divided into a plurality of time slots and comprising a first and second impulse on a first and second time slot. The system further comprises an integrator unit operable to receive the time domain signal on a time slot by time slot basis. The integrator unit is operable, to accumulate, on a time-slot-by-time-slot basis, an amplitude value corresponding to a running total of the sum of the amplitude of the impulse signals received, and accumulate, on a time-slot-by-time-slot basis, the accumulated amplitude value. The integrator unit is thereby operable to generate, after receipt of the time domain signal, a value which corresponds to the result of the multiply and add expression.

A system for evaluating a multiply and add expression. The system comprises an encoder for encoding variables of the multiply and add expression on a time domain signal divided into a plurality of time slots and comprising a first and second impulse on a first and second time slot. The system further comprises an integrator unit operable to receive the time domain signal on a time slot by time slot basis. The integrator unit is operable, to accumulate, on a time-slot-by-time-slot basis, an amplitude value corresponding to a running total of the sum of the amplitude of the impulse signals received, and accumulate, on a time-slot-by-time-slot basis, the accumulated amplitude value. The integrator unit is thereby operable to generate, after receipt of the time domain signal, a value which corresponds to the result of the multiply and add expression.

An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.