A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.

Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing.

The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

An electric vehicle motor rotational speed value generating device comprises: a first counter counting an input frequency according to a system frequency and outputs a first bit numerical value; a second counter receiving the first bit numerical value, the second counter counts the first bit numerical value with an exponent n in a 2.sup.n exponential function that approximates a maximum rotational speed command value and outputs a second bit numerical value; a frequency divider receiving the second bit numerical value, and the frequency divider divides the second bit numerical value from the system frequency and outputs a counting frequency; and a third counter receiving the counting frequency, and the third counter is electrically connected to a maximum frequency generator and receives a maximum frequency generated by the maximum frequency generator, and the third counter counts the maximum frequency from the counting frequency and outputs a feedback rotational speed value.

An electric vehicle motor rotational speed value generating device comprises: a first counter counting an input frequency according to a system frequency and outputs a first bit numerical value; a second counter receiving the first bit numerical value, the second counter counts the first bit numerical value with an exponent n in a 2.sup.n exponential function that approximates a maximum rotational speed command value and outputs a second bit numerical value; a frequency divider receiving the second bit numerical value, and the frequency divider divides the second bit numerical value from the system frequency and outputs a counting frequency; and a third counter receiving the counting frequency, and the third counter is electrically connected to a maximum frequency generator and receives a maximum frequency generated by the maximum frequency generator, and the third counter counts the maximum frequency from the counting frequency and outputs a feedback rotational speed value.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.