A k-cluster residue number system includes a processor and a memory. The processor is used to generate a modular set composed of p coprime integers, generate a dynamic range by taking a product of the p coprime integers, generate row indices for all integers in the dynamic range, generate column indices for all integers in the dynamic range, and generate a look-up table according to the row indices, the column indices and all integers in the dynamic set. The memory is used to store the look-up table. The p coprime integers include 2.

A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.

Systems and techniques that facilitate Hamiltonian simulation based on simultaneous-diagonalization are provided. In various embodiments, a partition component can partition one or more Pauli operators of a Hamiltonian into one or more subsets of commuting Pauli operators. In various embodiments, a diagonalization component can generate one or more simultaneous-diagonalization circuits corresponding to the one or more subsets. In various aspects, a one of the one or more simultaneous-diagonalization circuits can diagonalize the commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, an exponentiation component can generate one or more exponentiation circuits corresponding to the one or more subsets. In various aspects, a one of the one or more exponentiation circuits can exponentiate the simultaneously diagonalized commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, a simulation component can concatenate the one or more simultaneous-diagonalization circuits, the one or more exponentiation circuits, and one or more adjoints of the one or more simultaneous-diagonalization circuits of the one or more subsets to simulate a time evolution of the Hamiltonian.

Computer-implemented methods for locking a blockchain transaction based on undetermined data are described. The invention is implemented using a blockchain network. This may, for example, be the Bitcoin blockchain. A locking node may include a locking script in a blockchain transaction Node to lock a digital asset. The locking script includes a public key for a determined data source and instructions to cause a validating node executing the locking script to verify the source of data provided in an unlocking script by: a) generating a modified public key based on the public key for the determined data source and based on data defined in the unlocking script; and b) evaluating a cryptographic signature in the unlocking script based on the modified public key. The blockchain transaction containing the locking script is sent by the locking node to the blockchain network. The lock may be removed using a cryptographic signature generated from a private key modified based on the data.

Embodiments are directed to aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates. An embodiment of a system includes a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, generate a metadata block corresponding to the memory line, the metadata block comprising the error correction code for the memory line and at least one metadata bit, generate an aggregate GHASH corresponding to a region of memory comprising a cacheline set comprising at least the memory line, encode the first data blocks and the metadata block, encrypt the aggregate GHASH as an aggregate message authentication code (AMAC), provide the encoded first data blocks and the encoded metadata block for storage on a memory module comprising the memory line, and provide the AMAC for storage on a device separate from the memory module.

An operating method of a floating point operation circuit includes, in response to receiving a first instruction, generating a first output by performing a fused multiplication and addition operation on a first input, a second input, and a third input. The method further includes, in response to receiving a second instruction, generating a second output by inverting one input of a fourth input, a fifth input, and a sixth input. Generating the second output includes generating a transform factor and a simplified value from the one input.

Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: interface circuitry to receive a first value and a second value; selector circuitry to select a first subset of bits and a second subset of bits from the first value; multiplier circuitry to: multiply the first subset to the second value during a first compute cycle; and multiply the second subset to the second value during a second compute cycle; left shift circuitry to perform a bitwise shift with a product of the first subset and the second value during the second compute cycle; adder circuitry to add a product of the second subset and the second value to a result of the plurality of bitwise shift operations during the second compute cycle; and comparator circuitry to determine the result of the modular multiplication based on a result of the addition during the second compute cycle.

A recording medium stores a program causing a computer to execute a process including: setting, for each order having a condition that a contract count is designated, a polynomial having a contract count under the condition; representing an order status in which the orders are combined, with a polynomial on a finite field having a remainder obtained by dividing a coefficient of each term in a polynomial obtained by multiplying the polynomials corresponding to the orders; updating the polynomial on the finite field to a polynomial on a finite field representing an order status after a first order is combined, by multiplying the polynomial by a polynomial corresponding to the first order; and detecting an error in the polynomial after the update when a coefficient which is not 0 of a term in the polynomial before the update is 0 in the polynomial.

This disclosure is directed to generating a set of data elements for more secure encryption or more resilient decryption associated with generating a target set of conditional data elements. The target set of conditional data elements may fulfill a condition. Public keys associated with an encrypted message may be associated with conditional data elements of the target set of conditional data elements. By performing at least one cycle of decryption associated with the public keys, an encrypted message may be decrypted.

In an example a method includes retrieving, from a persistent memory, a previously-identified counter value corresponding to an iteration of a prime number generation procedure that previously produced a verified prime number. The method further includes re-generating, using processing circuitry implementing a deterministic prime number calculator and with the previously-identified counter value as an input to the deterministic prime number calculator, the verified prime number.