A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.

According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.

Certain aspects of the present disclosure provide techniques for privacy preserving sharing and validation of sensitive information in a computing environment. An example method generally includes generating a hashed value of a sensitive data item. A set of modulo values is calculated for the hashed value of the first sensitive data item using a set of prime numbers between an upper bound number and a lower bound number. A request to validate the first sensitive data item is transmitted to a target computing system. The request includes the set of prime numbers and the set of modulo values. An indication of whether a match was found for each respective modulo value in the set of modulo values is received from the target computing system, and a request associated with the first sensitive data item is processed based on the indication.

Certain aspects of the present disclosure provide techniques for privacy preserving sharing and validation of sensitive information in a computing environment. An example method generally includes generating a hashed value of a sensitive data item. A set of modulo values is calculated for the hashed value of the first sensitive data item using a set of prime numbers between an upper bound number and a lower bound number. A request to validate the first sensitive data item is transmitted to a target computing system. The request includes the set of prime numbers and the set of modulo values. An indication of whether a match was found for each respective modulo value in the set of modulo values is received from the target computing system, and a request associated with the first sensitive data item is processed based on the indication.

A system, method and computer-readable medium provide secure communication between a first and a second computer system based on supersingular isogeny elliptic curve cryptography. The first computer system and the second computer system each determine kernels K.sub.A and K.sub.B including computing mP+nQ by accessing a lookup table stored in a memory that contains a range of doubles of an end point of the respective kernels, where P and Q are points on the public elliptic curve and m and n are integers. The first computer system and the second computer system compute secret isogenies by determining a respective kernel K.sub.BA and K.sub.AB using mixed-base multiplicands with a single inversion, including computing the respective kernel K.sub.BA and K.sub.AB by converting the multiplicands to base 32, and computing scalar multiplications using the base 32 multiplicands.

In example implementations described herein, there are systems and methods for computation of force and moment in the time domain for a physical system including one or more sensors, which can involve obtaining material properties and first modal properties of the physical system; generating a material property matrix from the material properties and second modal properties from the obtained modal properties; measuring, via the sensors, a set of motion responses of the physical system; obtaining first quantities based on the second modal properties and the material property matrix; calculating a first intermediate matrix from the second modal properties and the set of motion responses; recursively computing, for each time step during measurement of the response, a second intermediate matrix based on (1) the first quantities, (2) the second modal properties, (3) the first intermediate matrix, and (4) a previously computed second intermediate matrix from at least one previous time step; and calculating the force and the moment for each time step during the measurement of the set of motion responses based on the second intermediate matrix and the second modal properties.

In example implementations described herein, there are systems and methods for computation of force and moment in the time domain for a physical system including one or more sensors, which can involve obtaining material properties and first modal properties of the physical system; generating a material property matrix from the material properties and second modal properties from the obtained modal properties; measuring, via the sensors, a set of motion responses of the physical system; obtaining first quantities based on the second modal properties and the material property matrix; calculating a first intermediate matrix from the second modal properties and the set of motion responses; recursively computing, for each time step during measurement of the response, a second intermediate matrix based on (1) the first quantities, (2) the second modal properties, (3) the first intermediate matrix, and (4) a previously computed second intermediate matrix from at least one previous time step; and calculating the force and the moment for each time step during the measurement of the set of motion responses based on the second intermediate matrix and the second modal properties.

One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.

The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.