A permutation algorithm using modular arithmetic is applied to the cells of one or more specific fields of a database or other file type. This permutation reorders the cells of the specific field(s) without altering content of any individual cell, thereby hiding relationships between cells of the permuted field(s) and the other information in the associated records. The permutation algorithm may use modular addition and modular subtraction, in either order. Different permutation algorithms may use varying numbers of parameters. To locate a specific cell in a permuted field, the parameter(s) from the permutation, an identification of the specific record associated with the cell, and an identification of the specific permuted field are applied in a modular arithmetic operation. A specific record with which a specific cell in a permuted field is associated may be obtained by an inverse modular arithmetic operation.

A permutation algorithm using modular arithmetic is applied to the cells of one or more specific fields of a database or other file type. This permutation reorders the cells of the specific field(s) without altering content of any individual cell, thereby hiding relationships between cells of the permuted field(s) and the other information in the associated records. The permutation algorithm may use modular addition and modular subtraction, in either order. Different permutation algorithms may use varying numbers of parameters. To locate a specific cell in a permuted field, the parameter(s) from the permutation, an identification of the specific record associated with the cell, and an identification of the specific permuted field are applied in a modular arithmetic operation. A specific record with which a specific cell in a permuted field is associated may be obtained by an inverse modular arithmetic operation.

Techniques for computing a multiplicative modular inverse of two numbers is described. In the case of a and p, p being an n-bit integer, computing the multiplicative modular inverse includes loading in a first register the value of a, and computing, using a first modular multiplier, a square of the first register n times. Concurrently, using a second modular multiplier, a.sup.n is computed. Further, a product of outputs from the first modular multiplier and the second modular multiplier is computed as a result of the multiplicative modular inverse of a and p. In cases where p has more than n bits, the multiplicative modular inverse is computed iteratively using n-bit windows.

Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.

A first share value and a second share value may be received. A combination of the first share value and the second share value may correspond to an exponent value. The value of a first register is updated using a first equation that is based on the first and second share values and the value of a second register is updated using a second equation that is based on the second share value. One of the value of the first register or the value of the second register is selected based on a bit value of the second share value.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Disclosed herein is an apparatus for calculating a cryptographic component R.sup.2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises an arithmetic logic unit configured to iteratively perform Montgomery multiplication of a first operand with a second operand to produce an intermediate result, wherein the first operand and the second operand are set to the intermediate result after each iteration, responsive to a termination condition being met, determine an adjustment parameter indicative of a difference between the intermediate result and the cryptographic component, and perform Montgomery multiplication of the intermediate result with the adjustment parameter, to calculate the cryptographic component for the cryptographic function.

Disclosed herein is an apparatus for calculating a cryptographic component R.sup.2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises an arithmetic logic unit configured to iteratively perform Montgomery multiplication of a first operand with a second operand to produce an intermediate result, wherein the first operand and the second operand are set to the intermediate result after each iteration, responsive to a termination condition being met, determine an adjustment parameter indicative of a difference between the intermediate result and the cryptographic component, and perform Montgomery multiplication of the intermediate result with the adjustment parameter, to calculate the cryptographic component for the cryptographic function.