Patent classifications
G06F7/764
Security system using keys encoded in holograms
A system for controlling access to secured resources using a security token having a hologram embossed thereon is provided. A key is split into a user key and a complimentary key based on a mask, wherein key values in the user key correspond to idle state values in the complimentary key and vice versa. The user key is used to generate a user key array, that is used to generate a three-dimensional virtual image that is holographically embossed onto a security token. The hologram is merged with a corresponding hologram for the complimentary key and the combination compared to an image of an ensemble of the key. The combination can be mergers of images or extractions of holograms. If a match is found, within a tolerance, an access grant signal is sent to the secure resources, thereby securing the resources based on presence of the security token.
CONSTANT TIME SECURE ARITHMETIC-TO-BOOLEAN MASK CONVERSION
A first arithmetic input share and a second arithmetic input share of an initial arithmetically-masked cryptographic value are received. A sequence of operations using the arithmetic input shares and a randomly generated number is performed, where a current operation in the sequence of operations generates a corresponding intermediate value that is used in a subsequent operation. At the end of the sequence of operations, a first Boolean output share and a second Boolean output share are generated. The arithmetic-to-Boolean mask conversion is independent of the input bit length.
CRYPTOGRAPHIC PROCESSING METHOD, RELATED ELECTRONIC DEVICE AND COMPUTER PROGRAM
A cryptographic processing method comprises the following steps: obtaining a second number determined by adding to a first number the order of a finite group or a multiple of this order; determining a quotient and a remainder by dividing the second number by a random number; obtaining a third element equal to the combination of elements equal to a first element of the finite group and in number equal to the product of the quotient and the random number; obtaining a fourth element equal to the combination of elements equal to the first element and in number equal to the remainder; determining a second element by combining the third element and the fourth element.
CROSS-DOMAIN ADAPTIVE LEARNING
Techniques for cross-domain adaptive learning are provided. A target domain feature extraction model is tuned from a source domain feature extraction model trained on a source data set, where the tuning is performed using a mask generation model trained on a target data set, and the tuning is performed using the target data set.
CAN FILTER COMBINING METHOD, DEVICE, AND CAN CONTROLLER
A (controller area network) CAN filter combining method and a CNA controller are provided. The CAN filter includes a special filter and one or more common filters. The method includes: initializing a mask code and at least two filter codes of the special filter, acquiring a first total number of the filter codes in the special filter and a second total number of the common filters, acquiring mask codes and filter codes of the common filters, and adjusting the mask code and the filter codes of the special filter on the basis of the first total number, the second total number, and the mask codes and the filtering codes of all of the common filters. The method reduces the load of a processor, and prevents the CAN controller from processing a large amount of irrelevant data, thereby accelerating communications.
Protection system and method
A device of executing a cryptographic operation on bit vectors, the execution of the cryptographic operation includes the execution of at least one arithmetic addition operation between a first operand and a second operand. Each operand comprises a set of components, each component corresponding to a given bit position of the operand. The device comprises a set of elementary adders, each elementary adder being associated with a given bit position of the operands and being configured to perform a bitwise addition between a component of the first operand at the given bit position and the corresponding component of the second operand at the given bit position using the carry generated by the computation performed by the elementary adder corresponding to the previous bit position. Each elementary adder has a sum output corresponding to the bitwise addition and a carry output, the result of the arithmetic addition operation being derived from the sum outputs provided by each elementary adder. The device is configured to apply a mask to each operand component input of at least some of the elementary adders using a masking logical operation, the mask being a random number.
INFORMATION PROCESSING APPARATUS, SECURE COMPUTATION METHOD, AND PROGRAM
There is provided an information processing apparatus that executes efficient type conversion processing in four-party computation using 2-out-of-4 replicated secret sharing. The information processing apparatus comprises a basic operation seed storage part, a reshare value computation part, and a share construction part. The basic operation seed storage part stores a seed for generating a random number used when computation is performed on a share. The reshare value computation part generates a random number using the seed, computes a share reshare value using the generated random number, and transmits data regarding the generated random number to other apparatuses. The share construction part constructs a share for type conversion using the data regarding the generated random number and the share reshare value received from other apparatuses.
Circuit and method for binary flag determination
The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.
Execution unit for calculations with masked data
According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations.
Statistical object generator
The present invention provides methods and apparatus to generate a statistical object, the deterministic statistical representation of an original object, using a Deterministic Random Bit Generator (DRBG) (10). Multiple DRBG Statistical Object Generators (10) may be chained together to increase security by using independent security configurations (22) for each DRBG Statistical Object Generator (10).