Cryptographic circuitry, in operation, conditionally swaps a first operand and a second operand of a cryptographic operation based on a control value. The conditional swapping includes setting a first mask of a number of bits and a second mask of the number of bits based on the control value, the first mask and the second mask being complementary and having a same Hamming weight. A result of a bitwise XOR operation on the first operand and the second operand is stored as a temporary value. A combination of bitwise logical operations are performed to conditionally swap the first operand and the second operand.

The disclosure relates to a 5.sup.th Generation (5G) or pre-5G communication system for supporting a higher data rate than a 4.sup.th Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a base station in a wireless communication system is provided. The apparatus includes: a master Field Programmable Gate Array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker coupled to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits assigned respectively to the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding respectively to the plurality of slave FPGAs.

A secure computation system comprises at least five secure computation server apparatuses connected to each other via a network and performs secure computation on a value stored while being secret-shared, and each of the secure computation server apparatuses has a comparative verification part that compares values, which should be the same, received from at least three secure computation server apparatuses and that accepts a received value identical to at least another received value as a correct value.

The disclosure relates to a 5.sup.th Generation (5G) or pre-5G communication system for supporting a higher data rate than a 4.sup.th Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a base station in a wireless communication system is provided. The apparatus includes: a master Field Programmable Gate Array (FPGA); a plurality of slave FPGAs controlled by the master FPGA; and an address masker coupled to the master FPGA and the plurality of slave FPGAs, wherein the address masker is configured to: receive different address bits assigned respectively to the plurality of slave FPGAs by the master FPGA; for the different address bits, mask bit values at a specific position with the same value; and transmit masked address bits corresponding respectively to the plurality of slave FPGAs.

Some embodiments are directed to an electronic computation device (100) arranged for obfuscated execution of a multiplication. The device comprises a storage (120) arranged for storing multiple variables used in the execution of an arithmetic operation, a variable (x: y; 2) of the multiple variables being represented as multiple multiplicative shares (X=(x.sub.0, x.sub.1, . . . , x.sub.m−1); Y=(y.sub.0, y.sub.1, . . . , y.sub.m−1); 20), said multiplicative shares being represented in the storage as multiple additive shares (x.sub.i=(x.sub.i,0,x.sub.i,1, . . . , x.sub.i,n−1); Yi=(y.sub.i,0,y.sub.i,1, . . . , y.sub.i,n−1); 210, 220).

A neural processor includes one or more neural engine circuits for performing convolution operations on input data corresponding to one or more tasks to generate output data. The neural engine circuits process the input data having a power-of-two (P2) shape. The neural processor circuit also includes a data processor circuit. The data processor circuit fetches source data having a non-power-of-two (NP2) shape. The source data may correspond to data of a machine learning model. The data processor circuit also reshapes the source data to generate reshaped source data with the P2 shape. The data processor circuit further sends the reshaped source data to the one or more neural engine circuits as the input data for performing convolution operations. In some cases, the data processor circuit may also perform padding on the source data before the source data is reshaped to the P2 shape.

Cryptographic circuitry, in operation, conditionally swaps a first operand and a second operand of a cryptographic operation based on a control value. The conditional swapping includes setting a first mask of a number of bits and a second mask of the number of bits based on the control value, the first mask and the second mask being complementary and having a same Hamming weight. A result of a bitwise XOR operation on the first operand and the second operand is stored as a temporary value. A combination of bitwise logical operations are performed to conditionally swap the first operand and the second operand.

A first input share value, a second input share value, and a third input share value may be received. The first input share value may be converted to a summation or subtraction between an input value and a combination of the second input share value and the third input share value. A random number value may be generated and combined with the second input share value and the third input share value to generate a combined value. Furthermore, a first output share value may be generated based on a combination of the converted first input share value, the combined value, and additional random number values.

A physically unclonable function (PUF) device is provided. The PUF device includes: a plurality of PUF cells configured to generate an output. Each of the plurality of cells includes a sense amplifier, a load circuit. The sense amplifier includes a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The sense amplifier having a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The first circuit generates an output at a first output node and the second circuit generates an output at the second output node. The load circuit having a first transistor and a second transistor configured to generate a bias to the sense amplifier to obtain a mask bit at a first output node and a second output node. The control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit. The harvester circuit includes a first transistor and a second transistor receives the input from the load and generates the difference in the input.

A device of executing a cryptographic operation on bit vectors, the execution of the cryptographic operation includes the execution of at least one arithmetic addition operation between a first operand and a second operand. Each operand comprises a set of components, each component corresponding to a given bit position of the operand. The device comprises a set of elementary adders, each elementary adder being associated with a given bit position of the operands and being configured to perform a bitwise addition between a component of the first operand at the given bit position and the corresponding component of the second operand at the given bit position using the carry generated by the computation performed by the elementary adder corresponding to the previous bit position. Each elementary adder has a sum output corresponding to the bitwise addition and a carry output, the result of the arithmetic addition operation being derived from the sum outputs provided by each elementary adder. The device is configured to apply a mask to each operand component input of at least some of the elementary adders using a masking logical operation, the mask being a random number.