A memory system comprising a qubit array configured to store therein one or more entangled qubit states encoded using a quantum stabilizer code. The memory system further comprises a quantum-state-refresh module configured to refresh an entangled qubit state in the qubit array when a degradation error is detected therein. The quantum-state-refresh module is further configured to detect the degradation error by performing a redundant measurement of a set of syndrome values corresponding to the quantum stabilizer code. The redundant measurement is based on an error-correction code defined using the generator matrix of the quantum stabilizer code and a corresponding supplemental parity-check matrix. In an example embodiment, each of the generator and supplemental parity-check matrices has a respective inclined-stripe form.

A memory system comprising a qubit array configured to store therein one or more entangled qubit states encoded using a quantum stabilizer code. The memory system further comprises a quantum-state-refresh module configured to refresh an entangled qubit state in the qubit array when a degradation error is detected therein. The quantum-state-refresh module is further configured to detect the degradation error by performing a redundant measurement of a set of syndrome values corresponding to the quantum stabilizer code. The redundant measurement is based on an error-correction code defined using the generator matrix of the quantum stabilizer code and a corresponding supplemental parity-check matrix. In an example embodiment, each of the generator and supplemental parity-check matrices has a respective inclined-stripe form.

A storage unit stores a flow matrix representing the flows between a plurality of entities to be assigned to a plurality of destinations, and a distance matrix representing the distances between the plurality of destinations. A processing unit calculates a first change in an evaluation function, which is to be caused by a first assignment change of exchanging the destinations of first and second entities among the plurality of entities, with vector arithmetic operations based on the flow and distance matrices, determines based on the first change whether to accept the first assignment change, and when determining to accept the first assignment change, updates an assignment state and updates the distance matrix by swapping the two columns or two rows (two columns in the example of FIG. 2) of the distance matrix corresponding to the first and second entities.

A storage unit stores a flow matrix representing the flows between a plurality of entities to be assigned to a plurality of destinations, and a distance matrix representing the distances between the plurality of destinations. A processing unit calculates a first change in an evaluation function, which is to be caused by a first assignment change of exchanging the destinations of first and second entities among the plurality of entities, with vector arithmetic operations based on the flow and distance matrices, determines based on the first change whether to accept the first assignment change, and when determining to accept the first assignment change, updates an assignment state and updates the distance matrix by swapping the two columns or two rows (two columns in the example of FIG. 2) of the distance matrix corresponding to the first and second entities.

A method of selecting, in hardware logic, an i.sup.th largest or a p.sup.th smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the r.sup.th iteration, the method comprises: summing an (m−r).sup.th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the r.sup.th bit of the selected number is determined and output and additionally the (m−r−1).sup.th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r).sup.th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

A method of selecting, in hardware logic, an i.sup.th largest or a p.sup.th smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the r.sup.th iteration, the method comprises: summing an (m−r).sup.th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the r.sup.th bit of the selected number is determined and output and additionally the (m−r−1).sup.th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r).sup.th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

A method for transferring data blocks from a field device to a server, each data block including data describing an operation of the field device during a block time period is provided. The method includes setting a first and a second pointer delimiting a completed time period; and, until a predetermined transfer period elapses: transferring the data blocks having a block time period that is later than the second pointer to the server in a chronological order; and if all data blocks having a block time period that is later than the second pointer have been transferred to the server, transferring the data blocks having a block time period that is earlier than the first pointer to the server in an anti-chronological order. Data blocks can efficiently and reliably be transferred to the server.

Disclosed are an apparatus and method for transforming a matrix, and a data processing system. The apparatus may include: a first shift unit, configured to receive matrix data and perform first cyclic shift on the matrix data to generate first data; a cache unit, configured to write each row of data into the cache unit in the first data thereto in an order different from the order of respective data in the row of data to store the first data as second data; and a second shift unit, configured to read the second data from the cache unit and perform second cyclic shift on the second data to generate transformed matrix data.

Disclosed are an apparatus and method for transforming a matrix, and a data processing system. The apparatus may include: a first shift unit, configured to receive matrix data and perform first cyclic shift on the matrix data to generate first data; a cache unit, configured to write each row of data into the cache unit in the first data thereto in an order different from the order of respective data in the row of data to store the first data as second data; and a second shift unit, configured to read the second data from the cache unit and perform second cyclic shift on the second data to generate transformed matrix data.

A training method, system, and computer program product include computing a matrix norm over a product of a weight matrix and a transpose of the weight matrix and using the matrix norm to constrain the L2 non-expansive neural network.