The transforming means 72 transforms first multidimensional data in which the number of elements of dimension of channel is C and the number of elements of each dimension other than the dimension of channel is 1 into second multidimension of a predetermined form. The channel dimension element number increase means 73 generates third multidimensional data in which the number of elements of the dimension of channel is increased from 1 to N, by performing a convolution layer process with a filter size of 1×1. The transposition means 74 performs transposition on the third multidimensional data so that the number of elements of the dimension of channel becomes C. The generation means 75 generates multidimensional data in which the number of elements of the dimension of channel is C and the number of elements of each dimension other than the dimension of channel is predetermined number of elements.

The transforming means 72 transforms first multidimensional data in which the number of elements of dimension of channel is C and the number of elements of each dimension other than the dimension of channel is 1 into second multidimension of a predetermined form. The channel dimension element number increase means 73 generates third multidimensional data in which the number of elements of the dimension of channel is increased from 1 to N, by performing a convolution layer process with a filter size of 1×1. The transposition means 74 performs transposition on the third multidimensional data so that the number of elements of the dimension of channel becomes C. The generation means 75 generates multidimensional data in which the number of elements of the dimension of channel is C and the number of elements of each dimension other than the dimension of channel is predetermined number of elements.

A device includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.

A device includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.

Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Embodiments of the present disclosure relate to indexing in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit directly coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs a convolution operation on input data to generate output data. The data processor circuit includes a buffer memory and an indexing circuit coupled to the buffer memory. The buffer memory stores an index tensor and the output data as a source tensor. The indexing circuit fetches a portion of the source tensor from the buffer memory by referencing the index tensor representing indexing information into the portion of the source tensor.

Embodiments of the present disclosure relate to indexing in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit directly coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs a convolution operation on input data to generate output data. The data processor circuit includes a buffer memory and an indexing circuit coupled to the buffer memory. The buffer memory stores an index tensor and the output data as a source tensor. The indexing circuit fetches a portion of the source tensor from the buffer memory by referencing the index tensor representing indexing information into the portion of the source tensor.

A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.