Aspects of the present invention disclose a method, computer program product, and system for parsing a domain-specific language (DSL) statement. The method includes one or more processors accessing a DSL statement that includes contracted phrases. The method further includes one or more processors identifying one or more contracted phrases in the DSL statement utilizing an annotated domain vocabulary for a DSL associated with the DSL statement and grammar rules for the DSL. The method further includes one or more processors determining expanded phrases corresponding to the identified one or more contracted phrases based on the annotated domain vocabulary and the grammar rules. The method further includes one or more processors creating an expanded abstract syntax tree (AST) that is representative of the DSL statement with the determined expanded phrases replacing the identified one or more contracted phrases.

Apparatus and methods related providing application execution information (AEI) are provided. A server can receive a request to provide a software package for a particular software application. The server can determine composite AEI (CAEI) for the particular software application. The CAEI can include a composite list of software with data about software methods of the particular software application executed by a computing device other than the server. The server can extract particular AEI related to the particular software application from the CAEI. The particular AEI can provide compiler hints for compiling at least one software method predicted to be executed by the particular software application. The server can generate the software package, where the software package can include the particular software application and the particular AEI. The server can provide the software package.

A device may receive source code and identify, based on the source code, an abstract syntax tree representing an abstract syntactic structure of the source code. Based on the abstract syntax tree, the device may identify a closure, the closure implementing a function based on at least a portion of the abstract syntax tree. In addition, the device may perform an action based on the closure.

Described herein are various computing technologies for various reverse engineering platforms capable of outputting a human readable and high level source code from various binary files in its original language, as developed before compilation. For example, a computer-implemented method includes generating, by a computer, an intermediate representation having machine-readable data representing assembly language for a binary file; detecting, by the computer, a set of one or more structural features by executing a convolutional neural network on the intermediate representation, the set of one or more structural features having one or more optimizations; identifying, by the computer, a set of one or more code transformations corresponding to the one or more optimizations detected in the set of one or more structural features; and generating, by the computer, one or more source code files representing the binary file according to the set of one or more code transformations.

A code completion system uses neural components to rank the unordered list of code completion candidates generated from an existing static analyzer. The candidates represent the next sequence of tokens likely to complete a partially-formed program element as a developer is typing in a software development tool. A re-ranking component generates a ranked order of the candidates based on a context embedding of the code context and candidate embeddings of the candidates, where both embeddings are based a common token encoding.

In some embodiments, there is provided a parser comprising at least one data processor; and at least one memory storing instructions which, when executed by the at least one data processor, result in operations comprising: receiving a line of text to be parsed; and processing, based on a configuration for the parser, the line of text into parsed text by at least: detecting one or more brackets and one or more separators in the text, determining a hierarchy for the text based on one or more parts, the one or more parts determined from the one or more brackets and one or more separators, and parsing, based on the hierarchy, the text to form the parsed text. Related systems and articles of manufacture are also provided.

A web-based application constructor can be used to construct a web display. A specification, for constructing a web display to contain page components that display data from heterogeneous data sources, may be created. The page components may be associated with uniform resource locators. Data from heterogeneous data sources may be retrieved to produce the web display. Display and update of the page components may be controlled using the uniform resource locators. User-selectable options may allow annotation of the page components for a page with comments.

A method is provided for validating a compiler-generated program portion that forms an optimized runnable code relative to an input runnable code. The method computes respective data sets used by the compiler-generated program portion. The respective data sets include (i) memory inputs UM, (ii) constant data memory areas UM_CONST, (iii) output memory areas DM, and (iv) output registers DR. The method copies the compiler-generated program portion to another memory area from a current memory area and appends a return instruction back to the current memory area at each exit point of the compiler-generated program portion. The method computes minimum and maximum base register offsets for base registers, from a union formed from a subset of the respective data sets. The method computes an allocation size for each of the base registers and an address assigned to each of the base registers. The method executes the copied compiler-generated program portion using (a) the minimum and maximum base register offsets, (b) the allocation size, and (c) the address assigned to each of the base registers, executes the input runnable code, examines results of the input runnable code in the output memory areas DM and of the compiler-generated program portion in the output registers DR, and indicates that the compiler-generated program portion is valid responsive to the results being identical.

Provided is a computing device according to an embodiment of the present disclosure including an integrated register file configured to store a first variable type and a first variable value of a first variable, and a second variable type and a second variable value of a second variable, a calculator configured to perform a first calculation on the first and second variables according to the first and second variable types, and output a first calculation result, and a type rule table comprising a plurality of entries and, when there is an entry corresponding to a type of the first calculation, and the first and second variable types, configured to output a type of the first calculation result.

A method is provided for validating a compiler-generated program portion that forms an optimized runnable code relative to an input runnable code. The method computes respective data sets used by the compiler-generated program portion. The respective data sets include (i) memory inputs UM, (ii) constant data memory areas UM_CONST, (iii) output memory areas DM, and (iv) output registers DR. The method copies the compiler-generated program portion to another memory area from a current memory area and appends a return instruction back to the current memory area at each exit point of the compiler-generated program portion. The method computes minimum and maximum base register offsets for base registers, from a union formed from a subset of the respective data sets. The method computes an allocation size for each of the base registers and an address assigned to each of the base registers. The method executes the copied compiler-generated program portion using (a) the minimum and maximum base register offsets, (b) the allocation size, and (c) the address assigned to each of the base registers, executes the input runnable code, examines results of the input runnable code in the output memory areas DM and of the compiler-generated program portion in the output registers DR, and indicates that the compiler-generated program portion is valid responsive to the results being identical.