Patent classifications
G06F8/41
Implementation for a heterogeneous device
Implementing a design for a heterogeneous device can include mapping, using computer hardware, a plurality of applications of a design for a device to a plurality of domains of the device, wherein each domain includes a different compute unit, performing, using the computer hardware, validity checking on the plurality of applications, detecting, using the computer hardware, a conflict between two or more of the plurality of applications from the validity checking, and, in response to the detecting, generating a notification of the conflict using the computer hardware. Operations such as automatically generating a boot image, debugging, and/or performing system level performance analysis may also be performed.
Eliminating dead stores
Dataflow optimization by dead store elimination focusing on logically dividing a contiguous storage area into different portions by use to allow a different number and type of dataflow and dead store techniques on each portion. A first storage portion, containing the storage for control flow related metadata, is split from a remaining storage portion. Liveness analysis is executed on the first storage portion using bitvectors with each bit representing four bytes. The remaining storage portion, containing the temporary storage for computational values, is processed using a deadness-range-based dataflow analysis. IN and OUT sets for each basic block are generated by processing blocks GEN and KILL sets by performing a backwards intersection dataflow analysis. Stores that write to the set of dead ranges in the IN sets of blocks are eliminated as dead stores.
Method and apparatus of code management
A method, apparatus, electronic device, storage medium and program product of code management are provided. In response to a request for building an executable file, corresponding developed code is obtained from a code library. The developed code is compiled into intermediate code to determine security of the intermediate code. In response to determining that the intermediate code is secure, an executable file is generated based on the intermediate code.
Method and apparatus of code management
A method, apparatus, electronic device, storage medium and program product of code management are provided. In response to a request for building an executable file, corresponding developed code is obtained from a code library. The developed code is compiled into intermediate code to determine security of the intermediate code. In response to determining that the intermediate code is secure, an executable file is generated based on the intermediate code.
Methods, controllers, and machine-readable storage media for automated commissioning of equipment
Tools and techniques are described to automate commissioning of physical spaces. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. Controllers also have access to databases of the physical space such that they can check that sensors in the space record the correct information for device activity, and sensors can cross-check each other for consistency. Once a physical space is commissioned, incentives can be sought based on commissioning results.
Method for merging architecture data
A computer-implemented method for merging architecture data that are exchanged between an architecture definition tool and a behavior modeling tool includes: opening a first file with first architecture data and a second file with second architecture data in a comparison tool; comparing the first architecture data with the second architecture data to obtain a first list of differences; retrieving at least one combination rule, wherein the at least one combination rule comprises an identification rule for identifying a difference and a change to be applied to the identified difference; ascertaining a second list of differences that fulfill the identification rule and removing the differences of the second list from the first list; and applying the change defined in the at least one combination rule to each difference in the second list.
Method for merging architecture data
A computer-implemented method for merging architecture data that are exchanged between an architecture definition tool and a behavior modeling tool includes: opening a first file with first architecture data and a second file with second architecture data in a comparison tool; comparing the first architecture data with the second architecture data to obtain a first list of differences; retrieving at least one combination rule, wherein the at least one combination rule comprises an identification rule for identifying a difference and a change to be applied to the identified difference; ascertaining a second list of differences that fulfill the identification rule and removing the differences of the second list from the first list; and applying the change defined in the at least one combination rule to each difference in the second list.
System and method for responsive process security classification and optimization
A system and method for the storage within one or more virtual execution context registers private code representative of processes or other information requiring an enhanced degree of security. The storage of the private code can be performed as a function of the type of code or in response to one or more markers embedded within the code. The time-variant nature of the virtual execution context registers affords a high degree of inherent security for the private code data stored within.
Architecture for virtual instructions
A system including a machine learning accelerator (MLA) hardware configured to perform machine-learning operations according to native instructions; an interpreter computing module configured to: generate, based on virtual instructions, machine language instructions configured to be processed by a processing hardware implementing the interpreter computing module; and cause the processing hardware to perform machine-learning operations according to the machine language instructions; and a compiler computing module associated with the MLA hardware, the compiler computing module configured to: receive instructions for performing an inference using a machine-learning model; based on the received instructions: generate the native instructions configured to be processed by the MLA hardware, the native instructions specifying first machine-learning operations associated with performing the inference; and generate the virtual instructions configured to be processed by the interpreter computing module, the virtual instructions specifying second machine-learning operations associated with performing the inference.
VERIFICATION OF A DATAFLOW REPRESENTATION OF A PROGRAM THROUGH STATIC TYPE-CHECKING
Functionality is described for providing a compiled program that can be executed in a parallel and a distributed manner by any selected runtime environment. The functionality includes a compiler module for producing the compiled program based on a dataflow representation of a program (i.e., a dataflow-expressed program). The dataflow-expressed program, in turn, includes a plurality of tasks that are connected together in a manner specified by a graph (such as a directed acyclic graph). The compiler module also involves performing static type-checking on the dataflow-expressed program to identify the presence of any mismatch errors in the dataflow-expressed program. By virtue of this approach, the above-described functionality can identify any errors in constructing the graph prior to its instantiation and execution in a runtime environment.