Methods, apparatus, systems, and articles of manufacture to determine an impact of a source code change on a cloud infrastructure are disclosed. One such system includes an infrastructure difference identifier to identify a difference between a proposed cloud infrastructure and an existing cloud infrastructure, and an infrastructure analyzer to (i) identify new infrastructure equipment to be added to the existing infrastructure based on the infrastructure modification, (ii) obtain identities some of the new infrastructure equipment that are candidates for right-sizing based on an infrastructure equipment grouping into which some of the new infrastructure equipment is to be placed, (iii) obtain information identifying a cost associated with different infrastructure equipment to deploy in place of the candidates, the different infrastructure equipment being right-sized for the grouping; and (iv) generate a report identifying an amount of savings that can be achieved by deploying the different infrastructure equipment in place of the new infrastructure equipment.

Methods, apparatus, systems, and articles of manufacture to determine an impact of a source code change on a cloud infrastructure are disclosed. One such system includes an infrastructure difference identifier to identify a difference between a proposed cloud infrastructure and an existing cloud infrastructure, and an infrastructure analyzer to (i) identify new infrastructure equipment to be added to the existing infrastructure based on the infrastructure modification, (ii) obtain identities some of the new infrastructure equipment that are candidates for right-sizing based on an infrastructure equipment grouping into which some of the new infrastructure equipment is to be placed, (iii) obtain information identifying a cost associated with different infrastructure equipment to deploy in place of the candidates, the different infrastructure equipment being right-sized for the grouping; and (iv) generate a report identifying an amount of savings that can be achieved by deploying the different infrastructure equipment in place of the new infrastructure equipment.

Embodiments disclosed herein relate to methods and systems for transliterating reasoning graphs and using the same to determine insights.

Embodiments disclosed herein relate to methods and systems for transliterating reasoning graphs and using the same to determine insights.

A system and method to translate source code in a source language executable in a source computing system to a target language executable in a target computing system. Source code in the source language is parsed to generate a corresponding parse tree containing at least one tree node and at least one leaf. During traversal of the parse tree, at least one mutation script is applied. The mutation script directs at least one of: generating a stream expression comprising at least one token corresponding to values of the at least one node and the at least one leaf of the parse tree; and formulating at least one text output containing a text pattern specified in the mutation script and/or values of the at least one token. Source code in the target language is outputted based on the at least one text output.

A system and method to translate source code in a source language executable in a source computing system to a target language executable in a target computing system. Source code in the source language is parsed to generate a corresponding parse tree containing at least one tree node and at least one leaf. During traversal of the parse tree, at least one mutation script is applied. The mutation script directs at least one of: generating a stream expression comprising at least one token corresponding to values of the at least one node and the at least one leaf of the parse tree; and formulating at least one text output containing a text pattern specified in the mutation script and/or values of the at least one token. Source code in the target language is outputted based on the at least one text output.

Training and/or utilization of a neural decompiler that can be used to generate, from a lower-level compiled representation, a target source code snippet in a target programming language. In some implementations, the lower-level compiled representation is generated by compiling a base source code snippet that is in a base programming language, thereby enabling translation of the base programming language (e.g., C++) to a target programming language (e.g., Python). In some of those implementations, output(s) from the neural decompiler indicate canonical representation(s) of variables. Technique(s) can be used to match those canonical representation(s) to variable(s) of the base source code snippet. In some implementations, multiple candidate target source code snippets are generated using the neural decompiler, and a subset (e.g., one) is selected based on evaluation(s).

Training and/or utilization of a neural decompiler that can be used to generate, from a lower-level compiled representation, a target source code snippet in a target programming language. In some implementations, the lower-level compiled representation is generated by compiling a base source code snippet that is in a base programming language, thereby enabling translation of the base programming language (e.g., C++) to a target programming language (e.g., Python). In some of those implementations, output(s) from the neural decompiler indicate canonical representation(s) of variables. Technique(s) can be used to match those canonical representation(s) to variable(s) of the base source code snippet. In some implementations, multiple candidate target source code snippets are generated using the neural decompiler, and a subset (e.g., one) is selected based on evaluation(s).

This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.

This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.