A method includes obtaining a copy of a first software executed by a first device in an industrial process control and automation system. The method also includes converting the first software to a second software. The second software is configured to perform functions of the first software. A programming language of the second software is different from a programming language of the first software, and the first and second software are designed for use with different operating systems. The method further includes providing the second software to a second device in the industrial process control and automation system for execution.

A method of localizing a computer program code comprises, with a manager node, updating a message catalog, localizing code at the manager node, and distributing the localize code to a number of client nodes. An apparatus for localizing computer program code comprises a processor, and a memory communicatively coupled to the processor, in which the memory comprises a message catalog, and in which the processor updates a message catalog, localizes code at the manager node, and distributes localized code to a number of client nodes.

Systems and methods for binary translation of executable code. An example binary translation method comprises: decoding a current source code fragment compatible with a source instruction set architecture (ISA); identifying a first source register referenced by the current source code fragment; determining that the first source register is not referenced by a register mapping table, wherein the register mapping table comprises a plurality of entries, each entry specifying a source register, a target register, and a weight value; identifying, among the plurality of mapping table entries, a mapping table entry comprising a highest weight value, wherein the identified mapping table entry specifies a second source register and a second target register; replacing, in the identified mapping table entry, an identifier of the second source register with an identifier of the first source register; and translating, using the mapping table entry, the current source code fragment into a target code fragment, wherein the target code fragment is compatible with a target ISA.

Systems and methods for binary translation of executable code. An example binary translation method comprises: decoding a current source code fragment compatible with a source instruction set architecture (ISA); identifying a first source register referenced by the current source code fragment; determining that the first source register is not referenced by a register mapping table, wherein the register mapping table comprises a plurality of entries, each entry specifying a source register, a target register, and a weight value; identifying, among the plurality of mapping table entries, a mapping table entry comprising a highest weight value, wherein the identified mapping table entry specifies a second source register and a second target register; replacing, in the identified mapping table entry, an identifier of the second source register with an identifier of the first source register; and translating, using the mapping table entry, the current source code fragment into a target code fragment, wherein the target code fragment is compatible with a target ISA.

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

A method for developing software in which the software comprises a plurality of programs. A change to a program is received. A data structure checking procedure may then be invoked. The changed program is parsed for a reference to a data structure. Other instances of the data structure are located in other programs within the software. The referenced data structure is compared to the located other instances of the data structure. A predefined action (such as notifying a programmer or correcting the inconsistencies) is performed in response to any detected differences between the referenced data structure and the located other instances of the data structure. These steps are repeated for all data structures within the changed program.

Systems and methods for improving the performance of mobile applications are disclosed. An exemplary method can include receiving a request for the application, where the request can include target device information. The method can also determine whether the application has been cached before. If the application has not been cached, the method can download the application as a bytecode and process the bytecode into the native code format, using an Ahead-of-time compiler. The method can also provide the application in the native code format to the target device over the network.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.