Patent classifications
G06F8/54
Systems and methods for policy linking and/or loading for secure initialization
A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.
Systems and methods for policy linking and/or loading for secure initialization
A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.
Systems and methods for array structure processing
A compiler optimization for structure peeling an array of structures (AOS) into a structure of arrays (SOA) by which a pointer to an array in the original program, is transformed into a tagged index that includes both an array index, and a memory identifier tagging the array index. Once processed by the compiler, each array index is identified by a respective memory identifier, hence if the program instructions call for redefining an array during run time, its array element can still be retrieved by referring to the memory identifier it is tagged with.
Program generation unit, information processing device, program generation method, and program
A program generation unit that generates voltage value information for making an LSI run on an operating voltage value based on a voltage context, wherein the program generation unit is provided with: a first compiler configured to compile a source program and that generate an object including a command sequence; a second compiler configured to generate the voltage value information based on a command density in the command sequence; and a linker configured to link the object with the voltage value information and that generates a user program.
Program generation unit, information processing device, program generation method, and program
A program generation unit that generates voltage value information for making an LSI run on an operating voltage value based on a voltage context, wherein the program generation unit is provided with: a first compiler configured to compile a source program and that generate an object including a command sequence; a second compiler configured to generate the voltage value information based on a command density in the command sequence; and a linker configured to link the object with the voltage value information and that generates a user program.
Configuration of secondary processors
Systems and methods are provided for configuration of a secondary processor by a host processor. The host processor can access compiled firmware for the secondary processor, which has a parameter stored at a pre-determined address. The host processor can modify the parameter at the pre-determined address in the firmware to generate a modified firmware for the secondary processor. The host processor can further load the modified firmware into a memory of the secondary processor. The secondary processor can execute the modified firmware having the modified parameter. The host processor can further remodify the parameter in the memory of the secondary processor during runtime without having to recompile the firmware.
Configuration of secondary processors
Systems and methods are provided for configuration of a secondary processor by a host processor. The host processor can access compiled firmware for the secondary processor, which has a parameter stored at a pre-determined address. The host processor can modify the parameter at the pre-determined address in the firmware to generate a modified firmware for the secondary processor. The host processor can further load the modified firmware into a memory of the secondary processor. The secondary processor can execute the modified firmware having the modified parameter. The host processor can further remodify the parameter in the memory of the secondary processor during runtime without having to recompile the firmware.
FAST COMPILING SOURCE CODE WITHOUT DEPENDENCIES
Techniques for an ultra-fact software compilation of source code are provided. A compiler receives software code and may divide it into code sections. A map of ordered nodes may be generated, such that each node in the map may include a code section and the order of the nodes indicates an execution order of the software code. Each code section may be compiled into an executable object in parallel and independently from other code sections. A binary executable may be generated by linking executable objects generated from the code sections. The methodology significantly differs from existing source code compilation techniques because conventional compilers build executable sequentially, whereas the embodiments divide the source code into multiple smaller code sections and compile them individually and in parallel. Compiling multiple code sections improves the compilations in order of magnitude from conventional techniques.
FAST COMPILING SOURCE CODE WITHOUT DEPENDENCIES
Techniques for an ultra-fact software compilation of source code are provided. A compiler receives software code and may divide it into code sections. A map of ordered nodes may be generated, such that each node in the map may include a code section and the order of the nodes indicates an execution order of the software code. Each code section may be compiled into an executable object in parallel and independently from other code sections. A binary executable may be generated by linking executable objects generated from the code sections. The methodology significantly differs from existing source code compilation techniques because conventional compilers build executable sequentially, whereas the embodiments divide the source code into multiple smaller code sections and compile them individually and in parallel. Compiling multiple code sections improves the compilations in order of magnitude from conventional techniques.
Semi-declarative method for infrastructure deployment and access control
A computer system includes a processor and a memory device. The computer system is configured to execute a function that builds a software instance definition object. The software instance definition object includes one or more configuration items, attributes, permissions, and linkages to other objects, which define a software instance. The computer system temporarily stores the software instance definition object in the memory device. The computer system updates at least one of the configuration items, attributes, permissions, and linkages to other objects of the stored software instance definition object, thereby creating an updated software instance definition object. A fix command is then executed to update the software instance based on the updated software instance definition object, thereby creating an updated software instance. After creating the updated software instance, the software instance definition object is deleted from the memory device.