A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.

Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

A method for executing a machine code using a microprocessor includes, after an operation of decoding a current loaded instruction, constructing a mask from the signals generated by an instruction decoder in response to decoding of the current loaded instruction by the decoder. The constructed mask varies as a function of the current loaded instruction. Subsequently, before an operation of decoding a next loaded instruction, the next loaded instruction is unmasked using the constructed mask.

A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Embodiments relate to a computer system, computer program product, and computer-implemented method to train a machine learning (ML) model using artificial intelligence to learn an association between (regulatory) compliance requirements and features of micro-service training datasets. The trained ML model is leveraged to determine the compliance requirements of a micro-service requiring classification. In an exemplary embodiment, once the micro-service has been classified with respect to applicable compliance requirements, the classified micro-service may be used as an additional micro-service training dataset to further train the ML model and thereby improve its performance.

Systems and methods are described that provide a backend micro-code architecture and a front-end user agent. For example, the user agent may accept an instruction that contains one or more components of an opcode. The backend system may receive the instruction and provide it to a bifurcated process. The first part of the process can decode the instruction and execute a series of search queries that correspond with the instruction. The second part of the process can receive the search results, create a data model/script that can be read by the user agent, and return/embed the data model/script to the user agent. The user agent may search the data model locally at the user device to reduce the number of electronic communications between the backend and front-end. The user agent can enable the user to dynamically create a new search by selecting different combination of the five components of an opcode.

Systems and methods are described that provide a backend micro-code architecture and a front-end user agent. For example, the user agent may accept an instruction that contains one or more components of an opcode. The backend system may receive the instruction and provide it to a bifurcated process. The first part of the process can decode the instruction and execute a series of search queries that correspond with the instruction. The second part of the process can receive the search results, create a data model/script that can be read by the user agent, and return/embed the data model/script to the user agent. The user agent may search the data model locally at the user device to reduce the number of electronic communications between the backend and front-end. The user agent can enable the user to dynamically create a new search by selecting different combination of the five components of an opcode.

A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.