Application code is obtained at a compiler toolchain, which accesses a package manager that tracks dependencies for a set of software components including application-level components represented as application-level packages, hypervisor interface-level components represented as hypervisor interface-level packages, and hypervisor-level components represented as hypervisor-level packages. A dependency solver is employed to select a sub-set of the set of packages that satisfy the dependencies. The sub-set of packages is assembled into an executable bundle, including a statically-linked binary built entirely from the sub-set of the selected packages that contains no external dependencies except calls to an interface defined entirely by the hypervisor interface-level packages, and a specialized monitor built entirely from the sub-set of the selected packages that runs on a standard operating system, loads and executes the statically-linked binary, and interacts with the statically-linked binary only through the interface defined by the hypervisor interface-level packages.

In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (μops), where a subset of the plurality of execution circuits are capable of execution of a fused μop; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer μops into fused μops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop. Other embodiments are described and claimed.

A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.