Methods and apparatus for adaptive integrity levels in electronic and programmable logic systems. In one example, an interface for communication between a first component and a second component is provided. The interface includes logic configured to change an integrity level for a communication from the first component to the second component during operation of the first component and the second component.

A recording medium stores a program causing a computer to execute a process including: setting, for each order having a condition that a contract count is designated, a polynomial having a contract count under the condition; representing an order status in which the orders are combined, with a polynomial on a finite field having a remainder obtained by dividing a coefficient of each term in a polynomial obtained by multiplying the polynomials corresponding to the orders; updating the polynomial on the finite field to a polynomial on a finite field representing an order status after a first order is combined, by multiplying the polynomial by a polynomial corresponding to the first order; and detecting an error in the polynomial after the update when a coefficient which is not 0 of a term in the polynomial before the update is 0 in the polynomial.

A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

An error rate measuring apparatus detects a bit error of input data returned from a device under test with transmission of a test signal at an error detector, and includes a log recording unit that records log data of state transition of each lane by handshakes of a plurality of lanes in a predetermined communication standard with respect to the device under test in making the device under test transit to a state of LOOPBACK, and a display unit that displays the recorded log data of the state transition of each lane in a time-series order.

A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

Systems and methods are provided for conducting incremental restore operations on block storage volumes using an object-based snapshot. A full restore from an object-based snapshot can include copying all blocks of a data set from the object-based snapshot to a destination volume. For high capacity volumes, full restores may take large amounts of time. Moreover, full restores may be inefficient where a destination volume already contains some data of the snapshot. Embodiments of the present disclosure provide for incremental restore operations, where a delta data set is transferred from the snapshot to the destination volume, representing data in the snapshot is not known to already exist on the volume or another available volume.

A system and method on one computer records actions on objects performed on a second computer. If an object is deleted from the second computer, the first computer can restore to a point in time the state of the object on the second computer, including assignments made between it and other objects, using the recorded actions.

A system and method on one computer records actions on objects performed on a second computer. If an object is deleted from the second computer, the first computer can restore to a point in time the state of the object on the second computer, including assignments made between it and other objects, using the recorded actions.