A method is provided for a hyper-converged storage-compute system to implement an active-active failover architecture for providing Internet Small Computer System Interface (iSCSI) target service. The method intelligently selects multiple hosts to become storage nodes that process iSCSI input/output (I/O) for a target. The method further enables iSCSI persistent reservation (PR) to handle iSCSI I/Os from multiple initiators.

A method may include obtaining a plurality of first data distributions in which each data distribution corresponds to running a first quantum circuit using a first input at a different noise level of a plurality of noise levels. The method may include simulating the first quantum circuit as a classical circuit and obtaining a noiseless data distribution corresponding to running the classical circuit using the first input. The method may also include determining an error mitigation parameter by performing a data regression analysis between the noiseless data distribution and the plurality of first data distributions. The method may additionally include obtaining a second data distribution that corresponds to running a second quantum circuit using a second input. A modified second data distribution may be obtained by applying the error mitigation parameter to the second data distribution such that noise included in the second data distribution is removed.

A secondary storage controller determines one or more tracks of one or more volumes in which data loss has occurred in the secondary storage controller. The secondary storage controller suspends a peer to peer remote copy operation between the secondary storage controller and a primary storage controller. Information on the one or more tracks of the one or more volumes in which the data loss has occurred is transmitted to the primary storage controller.

A control system includes: an image processing circuit; a first error detection circuit configured to perform first error detection on second image data; a first error code value generation circuit configured to generate a first error code value based on the second image data; a transmission interface circuit; a reception interface circuit; a second error code value generation circuit configured to generate a second error code value based on the second image data; a second error detection circuit configured to perform second error detection based on the first error code value and the second error code value; and a control circuit configured to output a control signal when an error is detected in at least one of the first error detection and the second error detection.

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

In a self-driving autonomous vehicle, a controller architecture includes multiple processors within the same box. Each processor monitors the others and takes appropriate safe action when needed. Some processors may run dormant or low priority redundant functions that become active when another processor is detected to have failed. The processors are independently powered and independently execute redundant algorithms from sensor data processing to actuation commands using different hardware capabilities (GPUs, processing cores, different input signals, etc.). Intentional hardware and software diversity improves fault tolerance. The resulting fault-tolerant/fail-operational system meets ISO26262 ASIL-D specifications based on a single electronic controller unit platform that can be used for self-driving vehicles.

Disclosed embodiments relate to adjusting vehicle Electronic Control Unit (ECU) software versions. Operations may include receiving a prompt to adjust an ECU of a vehicle from executing a first version of ECU software to a second version of ECU software; configuring, in response to the prompt and based on a delta file corresponding to the second version of ECU software, the second version of ECU software on the ECU in the vehicle for execution; and configuring, in response to the prompt, the first version of ECU software on the ECU in the vehicle to become non-executable.

A circuit device 100 includes an interface circuit 160 that receives image data and information for image check and a processing circuit 105 that performs image check processing. The information for image check includes information for designating an image check method for a region to be subjected to image check and position information of the region to be subjected to image check. The processing circuit 105 performs the image check processing on the image data of the region to be subjected to image check specified by the position information, using the image check method designated by the designation information.

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.