Mechanisms for reducing memory inconsistencies between two synchronized computing devices are provided. A first hypervisor module of a first computing device iteratively determines that content of a memory page of a plurality of memory pages has been modified. The content of the memory page is sent to a second hypervisor module on a second computing device. At least one other memory page of the plurality of memory pages is identified, and a verification value based on the content of the at least one other memory page is generated. The verification value and a memory page identifier that identifies the at least one other memory page is sent to the second hypervisor module on the second computing device.

The aircraft control systems and methods disclosed herein are configured to detect a residual error associated with a flight control computer of an aircraft and mitigate the effect(s) of such residual error in order to maintain safe operation of the aircraft. In some embodiments, the systems and methods are configured to detect an out-of-flight-envelope situation of the aircraft and determine whether or not the flight control computer is attempting to recover the aircraft from the out-of-flight-envelope situation. If the flight control computer is perceived as attempting to recover the aircraft from the out-of-flight-envelope situation, the flight control computer is permitted to continue controlling the aircraft. Otherwise, the excursion outside of the normal flight envelope is perceives as potentially having been caused by a residual error and the flight control computer is prevented from continuing to control the aircraft.

A disclosed storage management method includes detecting an unrecoverable failure associated with a logical block of a first physical storage device that is one of a plurality of storage devices within a redundant virtual drive that also includes a hot spare drive. Data for the unrecoverable block may be rebuilt from data in the remaining storage devices and stored in a logical block of the hot spare drive. One or more logical block maps may be maintained to identify unrecoverable logical blocks and to indicate the logical blocks and storage devices to which each of the unrecoverable logical blocks is relocated. I/O operations that access “good” logical blocks are normally while accesses to unrecoverable logical blocks are rerouted according to the logical block map. One or more unrecoverable thresholds may be supported to initiate operations to replace storage devices containing unrecoverable blocks exceeding an applicable threshold.

Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log2 calculators, exp2 calculators, logALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).

Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

An integrated circuit includes a built-in-self-test circuit that generates output test signals and a circuit tested by the built-in-self-test circuit. The circuit tested by the built-in-self-test circuit generates test results in response to the output test signals during a test. Pipeline register circuits are coupled together to form a signal path for transmitting the output test signals from the built-in-self-test circuit to the circuit tested by the built-in-self-test circuit. A functional circuit block is located in a reserved die area of the integrated circuit. The signal path is routed around the reserved die area to the circuit tested by the built-in-self-test circuit. At least a subset of the pipeline register circuits are located adjacent to at least two sides of the reserved die area.

A fault detection system includes a sensor configured to measure a physical quantity and generate a measurement of the physical quantity; a first processor configured to receive the measurement, execute a first firmware based on the measurement, and output a first result of the executed first firmware; a second processor configured to receive the measurement from the sensor, execute a second firmware based on the measurement, and output a second result of the executed second firmware, wherein the first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin; and a fault detection circuit configured to detect a fault when the first result and the second result are not within the predetermined margin.

Example distributed caching systems and methods are described. In one implementation, a system has multiple host systems, each of which includes a cache resource that is accessed by one or more consumers. A management server is coupled to the multiple host systems and presents available cache resources and resources associated with available host systems to a user. The management server receives a user selection of at least one available cache resource and at least one host system. The selected host system is then configured to share the selected cache resource.