A method and apparatus of performing fault tolerance in a fault tolerant computer system comprising: a primary node having a primary node processor; a secondary node having a secondary node processor, each node further comprising a respective memory; a respective checkpoint shim; each of the primary and secondary node further comprising: a respective non-virtual operating system (OS), the non-virtual OS comprising a respective; network driver; storage driver; and checkpoint engine; the method comprising the steps of: acting upon a request from a client by the respective OS of the primary and the secondary node, comparing the result obtained by the OS of the primary node and the secondary node by the network driver of the primary node for similarity, and if the comparison of indicates similarity less than a predetermined amount, the primary node network driver informs the primary node checkpoint engine to begin a checkpoint process.

The present application provides a method for planning a recovery resource for resisting N-time faults and an optical transmission device, and the method includes: planning, on an optical transmission device according to preset network planning information, a recovery resource for resisting (N−1)-time faults for preset (N−1)-time faults, and the recovery resource for resisting (N−1)-time faults is an optimal recovery resource corresponding to each interrupted service during the preset (N−1)-time faults; and planning, by the optical transmission device according to the network planning information and the recovery resource for resisting (N−1)-time faults, a recovery resource for resisting N-time faults for preset N-time faults, where the recovery resource for resisting N-time faults is a network-wide optimal recovery resource corresponding to interrupted services during the N-time faults. According to the present application, recovery resource costs can be reduced, and recovery resource planning reliability can be improved.

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device and initializing a timer associated with the block family. Responsive to beginning to program a block residing on the memory device, the processing device associates the block with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family; continues to program data to the block; and performs a hard closure of the block family in response to one of the timer reaching a hard closure value or the block family satisfying a hard closure criteria.

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

Certain embodiments may relate to providing increased storage capacity. For instance, a memory storage device may include a motherboard with an external communication interface. The memory storage device may also include a multiple solid-state drives coupled to the motherboard in communication with the external communication interface. Each of the plurality of solid-state drives may include a respective storage controller to manage the distribution of data during a write or read operation to a combination of a primary storage allocation and a redundant storage allocation. The redundant storage allocation may be included in the combination in response to detecting an error condition associated with at least a portion of the primary storage allocation.

Described herein is a method implemented by circuitry for providing fault tolerance in a combinational circuit. The circuitry identifies sensitive gates of the circuit that require protection from at least one of a first type of fault and a second type of fault. Further, circuitry computes for each first type of transistor included in the sensitive gate, a first failure probability, and for each second type of transistor included in the sensitive gate, a second failure probability. The circuitry calculates a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold to determine a protection type based on an area overhead constraint.

Provided herein are an acceleration system and a driving method thereof. The acceleration system includes a configuration memory, and a plurality of processing units which receive works from the configuration memory, perform the received works, and output results of the performed works. Each of the processing units include an n (n is an integer of three or more) number of processing elements which generate an n number of results, and each of which receives one of the works, and a select module which selects, using a majority-vote system, one of the n number of generated results and generates a selected result.

Data synchronization includes establishing a plurality of target data tables based on a source data table in which data to be synchronized is stored, determining a current target data table from the plurality of target data tables, synchronizing the source data table and the current target data table, and directing an application server to access the current target data table upon successful completion of synchronization.

A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.