Embodiments of the disclosure provide systems and methods for enabling disaster recovery from a source cluster to a target cluster in a multi-cluster cloud-computing environment. A domain cluster configures a replicated data volume to be updated with data from a data volume of the source cluster, wherein the replicated data volume resides in the target cluster; determines that the target cluster is to replace the source cluster as an active cluster; rebuilds, in the target cluster, a new container instance to replace the container instance on the source cluster; configures the container instance to utilize the replicated data volume in the target cluster; and discontinues recognition of the data volume and container instance on the source cluster as being authoritative.

Embodiments of the present disclosure provide a memory system and an operating method thereof. A memory system includes a memory device and a memory controller. The memory controller is configured to create a bad memory area replacement table including state information of a bad memory area among a plurality of memory areas, add the state information of one or more runtime bad memory areas to the bad memory area replacement table when one or more runtime bad memory areas occur, and remap, based on the bad memory area replacement table, a bad sub-area included in a target memory area to a normal sub-area included in one of remaining bad memory areas other than the target bad memory area among the bad memory areas added to the bad memory area replacement table.

Embodiments of the disclosure provide systems and methods for enabling disaster recovery from a source cluster to a target cluster in a multi-cluster cloud-computing environment. A domain cluster configures a replicated data volume to be updated with data from a data volume of the source cluster, wherein the replicated data volume resides in the target cluster; determines that the target cluster is to replace the source cluster as an active cluster; rebuilds, in the target cluster, a new container instance to replace the container instance on the source cluster; configures the container instance to utilize the replicated data volume in the target cluster; and discontinues recognition of the data volume and container instance on the source cluster as being authoritative.

An arrangement for redundant data processing has an integrated circuit in which the functionality of a multi-core processor is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program. The results which emerge from the execution of the useful program by the different processor cores are compared by a comparison module of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) that is assigned to the particular processor core. In terms of hardware, the individual processor cores are at least partially implemented separately in the integrated circuit.

The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.

In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.

A tool for performing remote part reseat actions. Responsive to receiving a request for a scheduled operation, the tool generates an operation table in a push file. Responsive to a determination that there is at least one redundant component for the scheduled operation, the tool identifies the at least one redundant component. The tool determines one or more tolerable errors for the at least one redundant component. The tool appends the at least one redundant component and the one or more tolerable errors to the operation table in the push file. The tool schedules the push file to prescribe one or more recovery operations for the scheduled operation.

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.