Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.

A sensor system may include first and second sensors configured to be coupled to a vehicle and generate respective first and second sensor signals indicative of operation of the vehicle. The sensor system may also include a sensor anomaly detector including an anomalous sensor model configured to receive the first and second sensor signals and determine that one or more of the first sensor or the second sensor is an anomalous sensor generating inaccurate sensor data. The sensor system may also be configured to identify one or more of the first sensor or the second sensor as the anomalous sensor generating inaccurate sensor data.

Aspects of the disclosure provide for reducing service disruptions in a computer system. A method of the disclosure may include identifying a plurality of services running on a node of a computer system, determining a plurality of priorities corresponding to the plurality of services, determining a plurality of service capacity factors for the plurality of services in view of the plurality of priorities, and determining a lost impact factor in view of the plurality of service capacity factors.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

In one aspect there is provided a method. The method may include collecting one or more functions that implement the decision logic of a solution. A snapshot of the one or more functions can be generated. The snapshot can executable code associated with the one or more functions. The solution can be deployed by at least storing the snapshot of the one or more functions to a repository Systems and articles of manufacture, including computer program products, are also provided.