Disclosed embodiments relate to generating an update package for updating software on an Electronic Control Unit (ECU) in a vehicle. Operations may include accessing a plurality of attributes of a software update to be stored on the ECU in the vehicle; accessing a corresponding plurality of attributes of current software stored on the ECU in the vehicle; comparing the plurality of attributes with the corresponding plurality of attributes; generating a delta file representing differences between the plurality of attributes and the corresponding plurality of attributes determined in the comparison; and providing the delta file to the ECU, wherein the delta file is configured to be processed by startup code in the ECU that enables the delta file to execute in the ECU in the vehicle.

Disclosed embodiments relate to performing updates to Electronic Control Unit (ECU) software while an ECU of a vehicle is operating. Operations may include receiving, at the vehicle while the ECU of the vehicle is operating, a software update file for the ECU software; writing, while the ECU is operating, the software update file into a first memory location in a memory of the ECU while simultaneously executing a code segment of existing code in a second memory location in the memory of the ECU; and updating a plurality of memory addresses associated with the memory of the ECU based on the software update file and without interrupting the execution of the code segment currently being executed in the second memory location in the memory of the ECU.

The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.

Embodiments perform configuration checking between data types of table fields, in order to determine mismatches therebetween. A configuration check request including a parameter identifying a system is received. A first data type is retrieved based upon the parameter. The first data type is compared with a second, different retrieved data type to determine a mismatch. In some embodiments the first data type and the second data type may be retrieved from different systems, with the mismatch revealing inter-system inconsistency. According to certain embodiments, the first data type and the second data type may be retrieved from a same system, with the mismatch revealing intra-system inconsistency. A configuration check report is generated from the mismatch and communicated to a user, for use in proactively correcting inconsistency. Embodiments may also retrieve values of the data types, as part of value help functionality.

An electronic apparatus is configured to generate current capability parameters associated with a software object executing on the electronic apparatus. The current capability parameters include an indication of resources required to execute the software object. The electronic apparatus determines whether the resources required to execute the software object are approaching a limit. The determination may be made by comparison to a threshold value. If the resources required to execute the software object are approaching the limit, then the electronic apparatus identifies a suitable target host based on the current capability parameters and initiates a migration of the software object to the suitable target.

Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

Techniques for managing node failures in container environments are disclosed. In one example, a method determines when a first node executing at least one containerized workload has failed. In response to determining the first node has failed, the method marks a configuration object for the first node with an indicator that the first node is not to be used to schedule execution of a subsequent containerized workload, isolates from the first node one or more storage volumes used by the first node, and deletes configuration objects for the one or more storage volumes and for the containerized workload. The method then causes creation of a replacement containerized workload for execution on a second node, removes one or more artifacts associated with the containerized workload from the first node, and removes the indicator from the configuration object for the first node.

A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.

A display device includes: a first memory storing compensation data and a display driver integrated chip including a compensator converting the input image data into output image data based on the compensation data. The display driver integrated chip includes: a second memory receiving the compensation data from the first memory when the display device is power-on; a third memory included in the compensator, the third memory storing the compensation data received from the second memory; and an error detector detecting an error in the compensation data stored in the third memory by comparing the compensation data stored in the first memory with the compensation data stored in the third memory.