G06F11/16

Flash memory architecture implementing interconnection redundancy

The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

System and method for multi-tier synchronization
11461196 · 2022-10-04 · ·

The present invention provides a System and method for multi-tiered data synchronization. Data is synchronized between a master synchronization server, one or more proxy synchronization servers, and client devices. Client devices establish synchronization sessions with either a proxy synchronization server or a master synchronization server, depending on which server provides the “best” available connection to that client device. Each proxy synchronization server synchronizes data with client devices that have established a synchronization session with such proxy synchronization server. The master synchronization server synchronizes data with client devices that have established a synchronization session with the master synchronization server. Each proxy synchronization server synchronizes data with the master synchronization server. Metadata associated with synchronized files is synchronized throughout the system in real-time. Files may be synchronized in real-time or of a delayed time.

Systems and methods for monitoring and responding to bus bit error ratio events

A computer system includes a bus interface having error correction capability. The bus interface includes an error register that is configured to provide error information related to correctable errors. System software within the computer system is configured to obtain the error information from the error register and calculate a bit error metric based on the error information. A baseboard management controller within the computer system is configured to take an action in response to obtaining the bit error metric from the system software and determining that a condition related to the bit error metric has been satisfied.

Transmission control method for HARQ in mobile communication system

A transmission control method for HARQ is provided for improving HARQ performance in a mobile communication system. The transmission control method for Hybrid Automatic Repeat reQuest (HARQ) in a mobile communication system according to the present invention includes receiving an downlink resource assignment message; determining whether configured downlink assignment has been indicated to an HARQ entity since a previously received downlink assignment for a User Equipment's (UE's) Cell-Radio Network Temporary Identifier (C-RNTI) for the same HARQ process; maintaining, if the configured downlink assignment has not been indicated to the HARQ entity, the HARQ process; and processing, if the configured downlink assignment has been indicated to the HARQ entity, the downlink resource assignment message as a resource assignment message for initial transmission.

Two-way real time communication system that allows asymmetric participation in conversations across multiple electronic platforms

Methods, systems, and apparatuses, including computer programs encoded on computer-readable media, for receiving a first communication request, from a web browser of a first user. A request for information is sent, using a first active communication protocol, to the web browser. A first communication as part of the first conversation is received from the first user. A responder sends a communication to the first user. A first conversation identifier is identified and used to store the conversation of the first user. The responder sends a communication to a second user. A second active communication protocol is determined and used to send the communication. A second conversation identifier is identified and used to store the conversation of the second user.

Mirrored remote procedure call cache

A method of operating a remote procedure call cache in a storage cluster is provided. The method includes receiving a remote procedure call at a first storage node having solid-state memory and writing information, relating to the remote procedure call, to a remote procedure call cache of the first storage node. The method includes mirroring the remote procedure call cache of the first storage node in a mirrored remote procedure call cache of a second storage node. A plurality of storage nodes and a storage cluster are also provided.

Memory repair method and apparatus based on error code tracking
11385959 · 2022-07-12 · ·

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

System and method for data replication using a single master failover protocol

A system that implements a data storage service may store data on behalf of storage service clients. The system may maintain data in multiple replicas of various partitions that are stored on respective computing nodes in the system. The system may employ a single master failover protocol, usable when a replica attempts to become the master replica for a replica group of which it is a member. Attempting to become the master replica may include acquiring a lock associated with the replica group, and gathering state information from the other replicas in the group. The state information may indicate whether another replica supports the attempt (in which case it is included in a failover quorum) or stores more recent data or metadata than the replica attempting to become the master (in which case synchronization may be required). If the failover quorum includes enough replicas, the replica may become the master.

SELF-HEALING LEARNING SYSTEM FOR ONE OR MORE CONTROLLERS
20220206784 · 2022-06-30 · ·

Disclosed embodiments relate to automatically providing updates to at least one vehicle, Operations may include receiving, at a server remote from the at least one vehicle, Electronic Control Unit (ECU) activity data from the at least one vehicle, the ECU activity data corresponding to actual operation of the ECU in the at least one vehicle; determining, at the server and based on the ECU activity data, a software vulnerability affecting the at least one vehicle, the software vulnerability being determined based on a deviation between the received ECU activity data and expected ECU activity data; identifying, at the server, an ECU software update based on the determined software vulnerability; and sending, from the server, a delta file configured to update software on tree ECU with a software update corresponding to the identified ECU software update.

System and method for logic functional redundancy

A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.