A multi-processor architecture for automated driving systems can be used to improve performance and provide design flexibility. For example, a multi-processor architecture can be used to implement command generation and safety functionality in different processors. The command generation processor can be a high performing processor compared with the safety processor. The safety processor can verify the safety of commands output from the command generation processor and provide additional I/O channels that are typically absent on high performing processors. Additionally, processing of some sensor data can be moved to expansion modules with additional processors to reduce bottlenecks and provide design flexibility for systems with different sensing requirements.

In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.

A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal if the first and second signatures do not match.

Embodiments of the present disclosure relate to a method and device for interleaving data in a wireless communication system. For example, a method of interleaving data in a wireless communication system comprises: determining, based on the number of a plurality of bits to be interleaved, a size of an interleaving array for interleaving the plurality of bits, wherein the number of rows is H and the number of columns is 2H-1 in the interleaving array; dividing the plurality of bits into a plurality of subsets based on the size of the interleaving array, such that an i-th subset of the plurality of subsets at most comprises 2(H-1-i)+1 consecutive bits, wherein i is a nonnegative integer smaller than H; writing the plurality of subsets respectively into the interleaving array, comprising for the i-th subset: writing an initial bit in the i-th subset into a position y(i, H-1) in an i-th row and an (H-1)-th column of the interleaving array; and writing subsequent bits of the initial bit respectively into subsequent rows of the i-th row, wherein at least two positions for writing the subsequent bits in an r-th row comprise y(r, H-1−(r-i)) and y(r, H-1+(r-i)); and reading the written plurality of bits successively column by column from the interleaving array.

A first server of a storage controller is configured to communicate with a host via a first bus interface, and a second server of the storage controller is configured to communicate with the host via a second bus interface. Data is written from the host via the first bus interface to a cache of the first server and via the second bus interface to a non-volatile storage of the second server. The data stored in the cache of the first server is periodically compared to the data stored in the non-volatile storage of the second server.

A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.

A high-availability network device database synchronization technique for devices configured with multiple network controllers is disclosed. An HA database that contains information regarding a network state may not properly synchronize upon failure of a network component. For example, an HA switch typically has only two controllers, an active and a standby. If there is a loss of the active controller that causes a failover, changes in the network state may occur rapidly while the system is trying to recover (e.g., process the failover action). In part, because of the impact of the failover (e.g., failed communication paths) and rapidity of changes to network state while processing the failover, database changes may not be properly synchronized across all available database instances. Disclosed techniques provide reconciliation of database values using a mark and sweep technique on the “upside” of the failover and alter the “source of truth” for data value discrepancies.

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

When barrier synchronization is executed between multiple nodes that include a node and execute processing for a same job, the node transmits first data indicating an intermediate result of processing of the node to another node with which processing of the node is to be synchronized first among the multiple nodes, and receives second data indicating an intermediate result of processing of the other node from the other node. The node stores the first data of the node in a first memory region of a memory provided for the node, and store the second data of the other node in a second memory region of the memory.

A computer system includes a BMC and a host of the BMC. The BMC receives a first message from a first remote device on a management network. The BMC determines whether the first message is directed to a storage service or fabric service executed on a main processor of a storage controller of the host. The host is a storage device. The storage controller includes an RDMA controller in communication with the main processor through an internal communication channel of the storage controller. The RDMA controller is managed by the storage service. The BMC extracts a service management command from the first message, when the first message is directed to the storage service or fabric service. The BMC sends, through a BMC communication channel established for communicating baseboard management commands between the BMC and the host, a second message containing the service management command to the host.