G06F11/16

METHOD OF USING A SINGLE CONTROLLER (ECU) FOR A FAULT-TOLERANT/FAIL-OPERATIONAL SELF-DRIVING SYSTEM

In a self-driving autonomous vehicle, a controller architecture includes multiple processors within the same box. Each processor monitors the others and takes appropriate safe action when needed, Some processors may run dormant or low priority redundant functions that become active when another processor is detected to have failed. The processors are independently powered and independently execute redundant algorithms from sensor data processing to actuation commands using different hardware capabilities (GPUs, processing cores, different input signals, etc.). Intentional hardware and software diversity improves fault tolerance. The resulting fault-tolerant/fail-operational system meets ISO26262 ASIL-D specifications based on a single electronic controller unit platform that can be used for self-driving vehicles.

Access request processing method and apparatus, and computer device
11301379 · 2022-04-12 · ·

An access request processing method is performed by a computer device that includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.

Disaster recovery of cloud resources

Embodiments of the present invention are directed to methods by which different services registered with cloud infrastructure may recover in case of disaster. Also directs procedures with which a resource provider may recover and rebuild its cloud resource information by scanning actual resources available. A resource provider will synchronize resources with a central service to get updated consumer and subscription information. In the scenario in which a central service fails and is recovered from backup, the central service should synchronize with resource providers to update its resource information.

Redundant processor architecture
11281547 · 2022-03-22 · ·

The present disclosure relates to an assembly including a first processor having a first core, a second core and a controller, and a second processor having a first core, and wherein the first core and the second core of the first processor, and the first core of the second processor are configured to execute a first procedure. The controller of the first processor is configured to compare a first result from executing the first procedure on the first core of the first processor with a second result from executing the first procedure on the second core of the first processor; and comparing each of the first and second results with a third result from executing the first procedure on the first core of the second processor, if the first and second results differ from one another.

Automatic firmware upgrade of an embedded node

This disclosure provides an apparatus and method for use in industrial control systems and other systems. A method includes detecting, by a primary node, that a backup node is available and unconfigured. The method includes automatically replicating, by the primary node, the primary node to the backup node, including replicating a personality of the primary node to the backup node.

Method, clock recovery module as well as computer program for recovering a clock signal from a data signal

A method for recovering a clock signal from a data signal by using a clock recovery module is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module as well as a computer program are described.

Distributed data object management system

In various embodiments, methods and systems for implementing distributed data object management are provided. The distributed data object management system includes a distributed storage system having a local metadata-consensus information store in and one or more remote metadata-consensus information stores. A metadata-consensus information store is configured to store metadata-consensus information. The metadata-consensus information corresponds to erasure coded fragments of a data object and instruct on how to manage the erasure coded fragments. The distributed storage system further includes a local data store and one or more remote data stores for the erasure coded fragments. The distributed data object management system includes a distributed data object manager for operations including, interface operations, configuration operations, write operations, read operations, delete operations, garbage collection operations and failure recovery operations. The distributed data object management system is operates based on metadata paths and data paths, operating in parallel, for write operations and read operations.

Workload repetition redundancy

A graphics processing system includes a plurality of processing units for processing tasks, each processing unit being configured to process a task independently from any other processing unit of the plurality of processing units; a check unit operable to form a signature which is characteristic of an output of a processing unit on processing a task; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is configured to process each task of a first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs, wherein the check unit is configured to form first and second signatures which are characteristic of, respectively, the first and second processed outputs, and wherein the fault detection unit is configured to compare the first and second signatures and raise a fault signal if the first and second signatures do not match.

Detecting anomalies online using historical controller processing activity
11288060 · 2022-03-29 · ·

Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.

Memory-based distributed processor architecture
11301340 · 2022-04-12 · ·

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.