Patent classifications
G06F11/16
FIELD PROGRAMMABLE GATE ARRAY (FPGA) FOR IMPROVING RELIABILITY OF KEY CONFIGURATION BITSTREAM BY REUSING BUFFER MEMORY
A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.
Reconstructing Data Segments in a Storage Network and Methods for Use Therewith
A processor in a storage network operates by: receiving an access request for a data segment, wherein the data segment is encoded utilizing an error correcting information dispersal algorithm as a set of encoded data slices that are stored in a plurality of storage units of the storage network and wherein each encoded data slice of the set of encoded data slices includes a corresponding checksum of a plurality of checksums; retrieving, from the storage network, a subset of encoded data slices that includes a threshold number of encoded data slices of the set of encoded data slices; determining, based on ones of the plurality of checksums corresponding to the subset of encoded data slices, when the subset of encoded data slices includes at least one corrupted encoded data slice; retrieving from at least one of the plurality of storage units an addition number of encoded data slices required to generate a reconstructed data segment based on the subset of encoded data slices; generating the reconstructed data segment in accordance with the error correcting information dispersal algorithm, using the additional number of encoded data slices and at least some of the subset of encoded data slices; providing the reconstructed data segment in response to the access request; forming a reconstructed set of encoded data slices utilizing the error correcting information dispersal algorithm on the reconstructed data segment; and replacing the at least one corrupted encoded data slice with at least one reconstructed encoded data slice of the reconstructed set of encoded data slices.
Use of cluster-level redundancy within a cluster of a distributed storage management system to address node-level errors
Systems and methods that make use of cluster-level redundancy within a distributed storage management system to address various node-level error scenarios are provided. According to one embodiment, a KV store of a node of a cluster of a distributed storage management system manages storage of data blocks as values and corresponding block IDs as keys. Data integrity errors are reported to the first node in the form of a list of missing block IDs that are in use but missing from the KV store. A metadata resynchronization process may then be caused to be performed, including for each block ID in the list of missing block IDs: (i) reading a data block corresponding to the block ID from another node of the cluster that maintains redundant information relating to the block ID; and (ii) restoring the block ID within the KV store by writing the data block to the node.
Vehicular apparatus
A vehicular apparatus is provided in which a plurality of operating systems each perform a display on a display device. The vehicular apparatus includes a controller unit. The controller unit is configured to implement a virtual environment to operate the plurality of operating systems. The controller is further configured to monitor and detect a malfunction in the display performed on the display device in the virtual environment, and to shield a display area where an incorrect display may be performed in response to the malfunction being detected.
Fault location in a redundant acquisition system
A method detects and localizes a failure of a measurement acquisition channel in an acquisition system including two redundant acquisition channels for the measurement of a physical quantity in an environment. The method uses a processor with a memory storing a model including modeled values of the physical quantity based on measurements of other physical quantities in the environment. The method includes detecting a symptomatic error of a defective acquisition channel when a deviation between the measured values of the two channels reaches a detection threshold, waiting to let the acquisition system evolve for a certain period, and localizing the defective channel among the two channels, when the deviation of the values measured between the channels reaches a localization threshold different from the detection threshold. The localization is made from the comparison of the measured value of each of the channels with a modeled value of the physical quantity.
Continuous replication and granular application level replication
A containerized environment and application that are configured for component specific continuous replication and granular application level application. A key value store, which stores key values related to configuration data of the containerized application, is replicated continuously to a replicated key value store at a replica site. Persistent volumes may also be replicated to a replica site. The replication can be performed to multiple replica sites in an application specific manner.
HOT UPDATES TO CONTROLLER SOFTWARE USING TOOL CHAIN
Disclosed embodiments relate to performing updates to Electronic Control Unit (ECU) software while an ECU of a vehicle is operating. Operations may include receiving, at the vehicle while the ECU of the vehicle is operating, a software update file for the ECU software; writing, while the ECU is operating, the software update file into a first memory location in a memory of the ECU while simultaneously executing a code segment of existing code in a second memory location in the memory of the ECU; and updating a plurality of memory addresses associated with the memory of the ECU based on the software update file and without interrupting the execution of the code segment currently being executed in the second memory location in the memory of the ECU.
DIVERSE INTEGRATED PROCESSING USING PROCESSORS AND DIVERSE FIRMWARE
A fault detection system includes a sensor configured to measure a physical quantity and generate a measurement of the physical quantity; a first processor configured to receive the measurement, execute a first firmware based on the measurement, and output a first result of the executed first firmware; a second processor configured to receive the measurement from the sensor, execute a second firmware based on the measurement, and output a second result of the executed second firmware, wherein the first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin; and a fault detection circuit configured to detect a fault when the first result and the second result are not within the predetermined margin.
Integrated circuit chip with cores asymmetrically oriented with respect to each other
An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
Integrated circuit chip with cores asymmetrically oriented with respect to each other
An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.