Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

A processor system comprises at least a program counter structure, an interrupt control device, a memory, and an apparatus. The interrupt control device is configured to respond to an interrupt request by providing the program counter structure with an address associated with the interrupt request. The program counter structure is configured to output the address to the memory via a memory interface. The apparatus is configured to protect the program counter structure in case of an interrupt request, the apparatus includes an interface, a comparing device, and an outputting device.

Each file storage apparatus of a plurality of file storage apparatuses stores a file system, and associates and stores paths of elements in the file system and archive destinations of the elements in an archive storage apparatus. When the file system is operated, each file storage apparatus transmits archive data of an element as an operation target, and operation information including operation details to the archive storage apparatus. The archive storage apparatus receives the archive data and the operation information, stores the archive data, and stores consistency information including the operation information and archive versions indicating a reception order of the operation information. A first file storage apparatus executes a synchronization process of acquiring the consistency information from the archive storage apparatus, correcting inconsistency between the acquired consistency information and consistency information including archive versions earlier than the acquired consistency information, and reflecting the file system on the consistency information.

An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

To achieve mutual monitoring of an operating state in consideration of an object storage. A calculator (10) according to the invention, which forms a cluster together with another calculator (20), includes a storage request unit (11) that requests an object storage (30) that manages data on an object-by-object basis to store first state information indicating a normal state of its own calculator, an acquisition request unit (12) that requests the object storage (30) to acquire second state information indicating a normal state of the other calculator (20), and a cluster control unit (13) that performs cluster control based on a result of storing the first state information and a result of acquiring the second state information, and when a result of acquiring the second state information is not the latest result, the acquisition request unit (12) requests acquisition of the second state information a specified number of times.

In some examples, an apparatus includes a housing and a mounting plate to fixably attach to the housing. The mounting plate has a central axis, a first end, a second end opposite the first end, a first lateral side extending axially from the first end to the second end, and a second lateral side extending axially from the first end to the second end. The mounting plate includes a shoulder and a first receptacle to slidingly receive a first tab on an end of an arm coupled to a display. The shoulder extends laterally from the first lateral side to the second lateral side and the first receptacle extends axially into the shoulder.