Provided are a device for providing a response operation corresponding to a device usage inquiry and a method of controlling the device. The method of controlling a device for providing a response operation corresponding to a device usage inquiry may include: receiving a user input corresponding to the device usage inquiry; classifying the device usage inquiry by analyzing the received user input corresponding to the device usage inquiry; extracting operation scenario information corresponding to a result of the classifying the device usage inquiry; and executing preset response operations of the device based on the operation scenario information, wherein the classifying includes classifying the device usage inquiry by inputting the user input of the device usage inquiry to a learning model that is a pre-generated.

A randomness testing apparatus is disclosed. A randomness testing apparatus according to an embodiment includes a randomness testing module to conduct a randomness test on physically unclonable function (PUF)-based hardware and a processing device to determine whether the PUF-based hardware is defective on the basis of a randomness test result.

A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.

The present disclosure provides a hard disk indicator circuit and a hard disk backplane. The hard disk indicator circuit includes an indicating unit, a control unit, a drive unit and a verification unit. The indicating unit indicates state of the hard disk. The control unit detects the state of the hard disk and outputting a control signal according to the state of the hard disk. The drive unit receives the control signal and lights the indicating unit according to the control signal. The verification unit obtains a level value of the indicating unit and determines whether the indicating unit is faulty according to the level value and the control signal. The present disclosure can quickly and accurately obtain the fault state of the hard disk indicator, save manpower and improve the fault detection efficiency.

Aspects include detecting, by an agent of a remote debugging tool that a first controller currently associated with the agent for a debugging session has not responded to a status inquiry from the agent. The first controller interacts with an end user, sends requests to the agent to operate a target program, and processes responses from the agent. Based on detecting that the first controller has not responded to the status inquiry from the agent, the agent identifies a second controller, associates the second controller with the agent for the debugging session, and resumes the debugging session with the second controller in place of the first controller. The associating includes synchronizing a debugging session state between the second controller and the agent. The target program continues to execute during the identifying, associating, and resuming, and the debugging session state is not changed by the identifying, associating, and resuming.

Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.

A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).

Example systems and related methods may relate to error detection in multi-threaded systems. Namely, a computing device includes a processor and a memory. The computing device also includes program instructions, stored in the memory, that upon execution by the processor cause the computing device to perform operations. The operations include receiving, by the processor, a communication signal. The communication signal initiates a first thread of at least two threads. The operations include sending, by the first thread via the processor, an inter-thread communication message to a second thread of the at least two threads. The operations include storing, in a trace log in the memory, information related to a state of the first thread and the inter-thread communication message. The operations include identifying an error location based on the information stored in the trace log.