A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.

Compatibility testing systems and methods are disclosed that provide scalable validation testing of systems and devices. In examples, systems and devices are identified to provide fundamental information about driver operations and driver extensions functionality. The identification allows systems and devices having particular similarities to be grouped in object groups. Compatibility tests are tagged as corresponding to the identifiable systems, devices, and/or object groups, compatibility testing system and methods map test sets specifically tailored to systems and devices as identified by their driver operations and driver extensions functionality. The tailored test sets include tests that ensure compatibility and through optimized test-to-device target mapping, an optimal set of testing set is discovered and scheduled to run. Strategically controlling the amount of testing distributed and executed increases compatibility testing speed and scalability.

A method is provided for diagnostic checking of a variable memory 14 in a safety critical system in order to detect variable memory failures; wherein the safety critical system comprises a central processing unit (CPU) with an operating system, an internal volatile memory 12 and an external volatile memory 14 including the variable memory 14; and the CPU can access a plurality of address spaces including one or more address spaces of the external volatile memory 14 that are utilised by the operating system and/or by a safety critical application of the safety critical system during normal use of the safety critical system.

A system and method are provided for testing features of an embedded system. The system includes a low-powered computing device communicatively coupled to a control application interface, a sensor interface, and a robotic interface. The low-powered computing device may receive sensor signals generated during a test, provide sensor data corresponding to the sensor signals, receive commands for the test, and provide instructions for movement of a robotic handler corresponding to at least one of the commands for the test. The system also includes a computing device communicatively coupled to the control application interface, an image processing interface, and a database interface. The computing device may receive sensor data, receive image data corresponding to images of the embedded system captured during the test, receive tests capable of being performed, and provide commands for the test.

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a non-transitory computer-readable medium having stored thereon a program of instructions executable by the processor. The program of instructions may be configured to, when read and executed by the processor, receive telemetry data associated with one or more information handling resources, receive failure statistics associated with the one or more information handling resources, and correlate the telemetry data and the failure statistics to create training data for a pattern recognition engine configured to predict a failure status of an information handling resource from operational data associated with the information handling resource.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Compatibility testing systems and methods are disclosed that provide scalable validation testing of systems and devices. In examples, systems and devices are identified to provide fundamental information about driver operations and driver extensions functionality. The identification allows systems and devices having particular similarities to be grouped in object groups. Compatibility tests are tagged as corresponding to the identifiable systems, devices, and/or object groups, compatibility testing system and methods map test sets specifically tailored to systems and devices as identified by their driver operations and driver extensions functionality. The tailored test sets include tests that ensure compatibility and through optimized test-to-device target mapping, an optimal set of testing set is discovered and scheduled to run. Strategically controlling the amount of testing distributed and executed increases compatibility testing speed and scalability.