A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.

A storage device includes a nonvolatile memory, a controller configured to control writing of data to the nonvolatile memory and reading of data from the nonvolatile memory in response to a request from a host, and a power module configured to receive power from the host. The controller is configured to transmit debugging data to the host through a channel connected to the host. The controller may be configured to transmit the debugging data to the host via at least one power line that is configurable for provision of power to the storage device.

Certain aspects of the present disclosure generally relate to memory training. An example method generally includes assigning each of a plurality of data channels of a memory device to at least one processor, performing memory tests, in parallel, on the plurality of data channels by at least in part performing read and write operations on at least two or more of the plurality of data channels in parallel using the at least one processor, and determining a setting for one or more memory interface parameters associated with the memory device relative to a data eye for each of the plurality of data channels determined based on the memory tests.

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.

A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

A method for testing storage protection hardware includes receiving by a non-trusted entity that is executing on a host server, a request to dispatch a secure entity. It is determined, by a secure interface control of the host server, whether the host server is in an auxiliary-secure (AS) debug mode for testing an AS entity. Based on determining that the host server is in the AS debug mode, a secure guest entity state is loaded from a state descriptor for the secure entity into an AS entity state in hardware to test, upon dispatch of the secure entity, accesses to pages in a memory that are registered as secure and as belonging to the AS entity.

The invention relates to a microchip with a multiplicity of reconfigurable test structures, wherein the microchip has a test input (TDI) and a test output (TDO), wherein the multiplicity of test structures can be connected to the test input (TDI) and the test output (TDO), wherein one intermediate memory is provided for each of the multiplicity of test structures, wherein each of the multiplicity of test structures can be tested separately and concurrently with the aid of the respective intermediate memory and a corresponding individual control.

Embodiments of information handling systems (IHSs) and methods are provided herein to automatically detect failure(s) on one or more power rails provided on a system motherboard of an IHS. One embodiment of such a method may include determining if a power rail test should be performed each time an information handling system (IHS) is powered on or rebooted. If a power rail test is performed, the method may perform a current measurement for each of the power rails separately to obtain actual current values for each power rail, compare the actual current values obtained for each power rail to expected current values stored for each power rail, and detect a failure on at least one of the power rails if the actual current value obtained for the at least one power rail differs from the expected current value stored for the at least one power rail by more than a predetermined percentage or amount.