The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

This disclosure concerns a medical device designed for delivering a medical fluid or designed for controlling delivery of a medical fluid, and to a method of operating such a medical device. The medical device comprises a user interface associated with an electronic circuit connected to a first port and to a second port of a controller. The electronic circuit enables the controller to detect actuation of the user interface. The controller is configured to execute the following sequence of steps: first step: configure the first port as an output port and to apply a first signal to the first port; second step: to acquire a second signal from the second port; and third step: to determine on the basis of the second signal if a short circuit has occurred and to generate a short circuit alert signal if applicable.

A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.

An enterprise disaster recovery system, including at least one data disk, a processor for running at least one data application that reads data from the at least one data disk and writes data to the at least one data disk over a period of time, a recovery test engine that (i) generates in parallel a plurality of processing stacks corresponding to a respective plurality of previous points in time within the period of time, each stack operative to process a command to read data at a designated address from a designated one of the at least one data disk and return data at the designated address in an image of the designated data disk at the previous point in time corresponding to the stack, and (ii) that generates in parallel a plurality of logs of commands issued by the at least one data application to write data into designated addresses of designated ones of the plurality of data disks, each log corresponding to a respective previous point in time, wherein the plurality of previous points in time within the period of time are specified arbitrarily by a user of the system.

Embodiments for automated testing of a virtualization management system are described. According to one aspect, a method includes generating a test case including a plurality of instances of commands and sending the test case to a plurality of interfaces supported by the virtualization management system. The method also includes generating a response file corresponding to each command in the test case. The method also includes comparing results from each interface to an instance of a command and in response to the results from each interface being identical, storing, the results in the response file corresponding to the command. The method also includes reporting an error in response to the results from each interface of the virtualization management system not being identical. The present document further describes examples of other aspects such as systems, computer products.

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.