A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

An integrated computing system configuration system includes a computing system that executes an application to receive a customized integrated computing system configuration having multiple design elements (DEs) that are associated with multiple components of a customized integrated computing system. The application may then, for at least DE, determine whether one or more other DEs in the customized integrated computing system configuration meet a specified criteria associated with the at least one DE, and when at least one of the other DEs does not meet the specified criteria such that the customized integrated computing system configuration comprises a invalid configuration, correct the invalid configuration by modifying one or more of the other DEs such that the customized integrated computing system configuration comprises a valid configuration.

An electronic device has a first terminal for receiving power from a connected external device, a second terminal for obtaining information of the external device, and a GND terminal connected to the second terminal. The electronic device causes a resistance between the second terminal and the GND terminal to change, and determines a type of the external device based on a voltage of the first terminal after the resistance is caused to change.

This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.

Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.

A disclosed method may include (i) initiating a cellular field testing tool that tests a condition of cellular network connectivity of a device under test, (ii) checking, prior to starting a specific test of the cellular field testing tool, whether each precondition in a set of preconditions is satisfied, and (iii) preventing the cellular field testing tool from starting the specific test until each precondition in the set of preconditions is satisfied. Related systems and computer-readable mediums are further disclosed.

A computer device and a memory startup method of a computer are provided, where a basic input/output system initializes only a first part of memory in a memory initialization phase after a computer is powered on and started, so that an operating system can be started, and after the operating system is started, the basic input/output system continues to initialize memory that is not initialized in the computer, so that, in a startup phase, the computer can start the operating system without needing to wait until all memory has been initialized; therefore, a time from being started to entering the operating system is reduced for the computer, and a user can quickly enter the operating system to perform an operation, thereby improving user experience.

A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.