G06F11/2268

Error rate measurement apparatus and error rate measurement method
12253924 · 2025-03-18 · ·

An error rate measurement apparatus includes an operation display unit and a display control unit. Displays a measurement result when the matrix scan function is executed. The display control unit displays a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value, uses each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected table as the cell, displays an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix, and identifies and displays the bit error rate for each cell on the display screen according to an error degree.

IDENTIFYING FAILURE MECHANISMS BASED ON A POPULATION OF SCAN DIAGNOSTIC REPORTS
20170052861 · 2017-02-23 · ·

Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. The failure mechanisms can be identified based on the topic distributions for the portions of the scan diagnostic reports and the feature distributions for the topics.

Utility to instantly protect sensitive information for an application log at runtime
09552272 · 2017-01-24 · ·

A computing system intercepts a message generated by an application at runtime. The message has content to be logged in a log data store. The computing system identifies sensitive information in the message content and modifies the message content to protect the sensitive information. The computing system causes the modified message content to be logged in the log data store.

SELF-CONTAINED AND CONFIGURABLE DEBUGGING MECHANISM FOR STREAM-BASED HARDWARE ACCELERATORS

A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

Intuitive Defect Prevention with Swarm Learning Intelligence over Blockchain Network

Aspects of the disclosure relate to s computing system that is configured to use heuristic and/or metaheuristic algorithms based on swarm learning (SL) intelligence frameworks and combine SL with blockchain and edge computing frameworks to provide a technologically efficient, responsive, and/or adaptable solution to detecting and preventing defects in software applications.

Method, an all-in-one tester and computer program product

There are disclosed various methods, apparatuses and computer program products for a testing apparatus. In accordance with an embodiment the testing apparatus has a frame; a gripping head for gripping a device to be tested; a first movement element for moving the gripping head with respect to the frame; a movement detector to detect at least one of a location and a position of the device; a touching element for touching the device; an imaging device for capturing images of the device; a display for generating visual information for capturing by the device; a set of sensors for examining operations of the device; a set of actuators for providing signals for reception by the device; and a set of plugs adapted to be inserted into a socket of the device.

TECHNIQUES FOR MONITORING RESOURCE CIRCUIT HEALTH
20250199926 · 2025-06-19 ·

Techniques for monitoring the health of resource circuits are described.

SUSPECTED ABNORMAL LOG DIAGNOSIS
20250208961 · 2025-06-26 ·

An approach for collecting diagnostic information, associated with a software system, based on identifying an abnormal log. The approach predicts a first time interval associated with a current log message based on one or more trained models and a first previous log message. The approach determines if a log is a suspected abnormal log based on the time interval. The approach, responsive to the log being a suspected abnormal log, executes actions of collecting additional diagnostic information based on a baseline diagnostic information collection rate, determines if the log is no longer a suspected abnormal log based at least on a second time interval. The approach, responsive to the log no longer being a suspected abnormal log, returns to the baseline diagnostic information collection rate.

APPARATUS AND METHOD FOR AUTOMATICALLY COLLECTING RESEARCH DATA

Provided is a collecting apparatus. The collecting apparatus may include: a collector collecting test data generated in a specific test space; a data server keeping the test data generated in the specific test space, and a handler of an administrator.

TRACE-BASED TESTING WITH SOFTWARE ACCESS POINTS

Testing techniques are disclosed. A test environment is accessed. The test environment includes a trace encoder and a software device-under-test interface (SDI). The SDI is coupled to a device-under-test (DUT). Software access points are inserted into the SDI to allow observability of one or more internal signals within the SDI. Modification instructions that cause the SDI to autonomously alter a response to the DUT are programmed into the SDI. The modification instructions are based on a test instruction set architecture. A test sequence is sent to the SDI, causing communications with the device under test. Replies are received from the DUT. The SDI responds to the replies and sends additional communications to the device under test. Additional replies are obtained from the DUT. A trace encoder creates a logic trace comprised of the states of the software access points.