Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.

Several methods may be used to exploit the natural physical variations of sensors, to generate cryptographic physically unclonable functions (PUF) that may strengthen the cybersecurity of microelectronic systems. One method comprises extracting a stream of bits from the calibration table of each sensor to generate reference patterns, called PUF challenges, which can be stored in secure servers. The authentication of the sensor is positive when the data streams that are generated on demand, called PUF responses, match the challenges. To prevent a malicious party from generating responses, instructions may be added as part of the PUF challenges to define which parts of the calibration tables are to be used for response generation. Another method is based on differential sensors, one of them having the calibration module disconnected. The response to a physical or chemical signal of such a sensor may then be used to authenticate a specific pair of sensors.

A device configured to periodically monitor operational activity of hardware components within a computing system infrastructure. The device is further configured to detect an issue that is associated with a hardware component, to identify commands that are sent to the hardware component to resolve the first issue, and to identify a test environment configuration for simulating the effect of sending the commands to the hardware component on the computing system infrastructure. The device is further configured to generate a solution script based on the identified commands and a testing script based on the identified test environment configuration, and to store an association between the first issue, the solution script, and the testing script in a script map.

PCIe devices may be connected to a test system for development, quality assurance, manufacturing, design validation, qualification, certification, and other testing. PCIe bus or other unexpected errors can avoid direct capture by the test system. Inserting a PCIe analyzer can capture a trace of PCIe bus data around any specific trigger. Due to the high volume and speed of data crossing the data bus when testing multiple devices, finding a correct trigger for an analyzer trace capture is akin to finding a needle in a haystack. By configuring a specific trigger pattern that the test system can send across the PCIe bus without impacting any of the devices under test, the test system can trigger the analyzer at the precise time needed to capture a PCIe bus data trace around the error.

A method to securely collect diagnostic information from an IT product is disclosed. In one embodiment, such a method includes contacting, by an IT product, an external service provider. Upon contacting the external service provider, the IT product checks a database of the external service provider to determine if diagnostic information associated with the IT product needs to be collected. If diagnostic information needs to be collected, an authorization request is sent to an administrator of the IT product. If the authorization request is approved, the IT product collects the diagnostic information and transmits the diagnostic information to the external service provider. A corresponding system and computer program product are also disclosed.

A method for testing a technical system. The method includes: tests are carried out with the aid of a simulation of the system, the tests are evaluated with respect to a fulfillment measure of a quantitative requirement on the system and an error measure of the simulation, on the basis of the fulfillment measure and error measure, a classification of the tests as either reliable or unreliable is carried out, and a test database is improved on the basis of the classification.

A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.

A test apparatus is provided for use with a mainframe and an adapter. The test apparatus includes a logical adapter interface unit and a control system. The logical adapter interface unit is interposable between the adapter and the mainframe whereby an I/O signal transmittable from the adapter and to the mainframe is transmitted through the logical adapter interface unit. The logical adapter interface unit is configured to manipulate the I/O signal. The control system is coupled to the logical adapter interface unit and the mainframe and is configured to control manipulations of the I/O signal by the logical adapter interface unit to mimic a condition of I/O traffic being run through the adapter and to log a response of the mainframe to the manipulations.

Systems, methods and computer program products are provided. An indication that a log of data entries has reached a size limit for the log is received. The data entries are continually stored in the log over time, and each entry comprises an associated log level. A threshold log level for data entries in the log is determined. At least one new data entry for the log is received. An existing data entry having a log level less than or equal to the threshold log level is overwritten by the new data entry, so that the size limit is not exceeded.

A fault indicator diagnostic system and fault indicator diagnostic method, with which a fault indicator of a machine can be more accurately diagnosed, has an operation sensor data table which indicates an association between sensor data and an acquisition time of the sensor data. An operation mode data table indicates an association between an operation mode and a time of operation in the operation mode. An operation data table is created by merge processing the operation sensor data table and the operation mode data table comprising the sensor data with regard to the operation mode at a given time. The system compares, in a given operation mode, a threshold determined on the basis of a diagnostic model created by learning from normal sensor data with a value computed on the basis of the diagnostic model from the sensor data to be diagnosed, and determines whether a malfunction is occurring.