Apparatus, methods, and other embodiments associated with debugging a device-under-test are disclosed. In one embodiment, a method includes sensing and recording a screen image produced by a device-under-test as the device-under-test is being operated. The sensing and recording of the screen image are performed by an apparatus. The method also includes sensing and recording coordinates and durations of gestures impinged upon the apparatus while operating the device-under-test. The sensing and recording of the coordinates and durations are performed by the apparatus. The apparatus is configured to physically conform to the device-under-test to allow functionality of the device-under-test through the apparatus.

A method for automatic error diagnosis in a test environment is provided. The method comprises the step of providing a plurality of test logs associated with known types of failures, each comprising a set of files. The method further comprises the step of arranging the plurality of test logs in a defect database. Moreover, the method comprises the step of transforming the set of files of the plurality of test logs into vectors adapted to be fed into a machine learning model.

A system includes an input for accepting a dataset including at least two sets of data in a dataset domain and one or more processors configured to derive at least two principal components from the dataset using principal component analysis, the at least two principal components being orthogonal to one another, map the dataset to a principal component domain derived from the at least two principal components, generate additional data in the principal component domain, and remap the additional data in the principal component domain back to the dataset domain as a newly generated dataset. Methods of operation and description of storage media, the operation of which performs the above operations, are also described.

A system includes a host and a display. The host includes a programmable logic device (PIP), a baseboard management controller (BMC) and a switch. The PLD performs a power-on procedure based on a power-on sequence code, generates variable character information in the power-on procedure, and fills the variable character information into a variable field in a preset log text file to result in an updated log text file. When it is determined that the power-on procedure is not normally completed, the PLD controls the switch to switch to a debug mode, and transmits a video signal containing debug information corresponding to the updated log text file to the switch so that the video signal is outputted to the display.

A method (100) of automated identification of one or more malfunction areas of a set (S) of malfunction areas for a service case in which a medical device (12) is serviced includes: generating an output probability vector (40) of probabilities for the set of malfunction areas of the medical device by operations including applying at least one classifier (42, 46) to at least one of (1) text descriptions of parts ordered for the service case and/or (2) a text description of the service case; and displaying a list (56) of one or more most probable malfunction areas for the service case wherein the one or more most probable malfunction areas are the one or more most malfunction areas of the set of malfunction areas having highest probability in the output probability vector.

A method and apparatus for data analysis according to various aspects of the present invention is configured to test a set of components and generate test data for the components. A diagnostic system automatically analyzes the test data to identify a characteristic of a component fabrication process by recognizing a pattern in the test data and classifying the pattern using a neural network.

Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

An S.M.A.R.T. threshold optimization method used for disk failure detection includes the steps of: analyzing S.M.A.R.T. attributes based on correlation between S.M.A.R.T. attribute information about plural failed and non-failed disks and failure information and sieving out weakly correlated attributes and/or strongly correlated attributes; and setting threshold intervals, multivariate thresholds and/or native thresholds corresponding to the S.M.A.R.T. attributes based on distribution patterns of the strongly or weakly correlated attributes. As compared to reactive fault tolerance, the disclosed method has no negative effects on reading and writing performance of disks and performance of storage systems as a whole. As compared to the known methods that use native disk S.M.A.R.T. thresholds, the disclosed method significantly improves disk failure detection rate with a low false alarm rate. As compared to disk failure forecast based on machine learning algorithm, the disclosed method has good interpretability and allows easy adjustment of its forecast performance.

Systems and methods described herein provide for testing and debugging different subsystems of an embedded controller using a testing architecture. The testing architecture can simulate messaging interfaces between internal subsystems of the embedded controller and external subsystems the controllers interacts with to integrate various types of software. A method includes generating test support models for one or more subsystems and establishing a communications network between the test support models and a control module of the embedded controller. A clock signal is generated to initiate processing within the testing architecture between the control module and the test support models. An event model is executed at the test support models using the clock signal and data is generated at one or more of the test support models responsive to the event model. The data can correspond to operational parameters of a respective system the embedded controller.

A system and method for presenting information related to an operation of a chip may include obtaining an input file including entries that record an operation of a chip; based on at least one parameter, identifying at least one pattern of entries in the input file; and based on analyzing a plurality of occurrences of the pattern, selecting an occurrence of the pattern that records a root cause of a problem.