Several methods may be used to exploit the natural physical variations of sensors, to generate cryptographic physically unclonable functions (PUF) that may strengthen the cybersecurity of microelectronic systems. One method comprises extracting a stream of bits from the calibration table of each sensor to generate reference patterns, called PUF challenges, which can be stored in secure servers. The authentication of the sensor is positive when the data streams that are generated on demand, called PUF responses, match the challenges. To prevent a malicious party from generating responses, instructions may be added as part of the PUF challenges to define which parts of the calibration tables are to be used for response generation. Another method is based on differential sensors, one of them having the calibration module disconnected. The response to a physical or chemical signal of such a sensor may then be used to authenticate a specific pair of sensors.

An operation management apparatus includes: a registration unit configured to register definition information defining an item of monitoring target information in an operation system; a generation unit configured to generate an expected value table and an actual setting value table each including a column corresponding to the item; a storage unit configured to store an expected value corresponding to the item input from an outside in the column in the expected value table, and store an actual setting value corresponding to the item contained in the monitoring target information in the column in the actual setting value table; a determination unit configured to compare the expected value with the actual setting value to determine whether they match or not; and an instruction unit configured to perform an update instruction for the operation system from the actual setting value to the expected value when they do not match.

Apparatus, methods, and other embodiments associated with debugging a device-under-test are disclosed. In one embodiment, a method includes sensing and recording a screen image produced by a device-under-test as the device-under-test is being operated. The sensing and recording of the screen image are performed by an apparatus. The method also includes sensing and recording coordinates and durations of gestures impinged upon the apparatus while operating the device-under-test. The sensing and recording of the coordinates and durations are performed by the apparatus. The apparatus is configured to physically conform to the device-under-test to allow functionality of the device-under-test through the apparatus.

A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.

Computing systems, devices, and methods for performing a virtual load test are disclosed herein. In accordance with the present disclosure, an asset data platform may define a respective range of acceptable values for each load-test variable in a set of load-test variables. The asset data platform may then receive one or more under-load reports from a given asset, and carry out a virtual load test for the given asset by, performing a comparison between the respective observation value for the load-test variable included in the most recent under-load report and the respective range of acceptable values for the load-test variable. In turn, the asset data platform may identify load-test variables for which the respective observation value falls outside of the respective range of acceptable values, and may then cause a client station to present results of the virtual load test for the given asset.

A storage device is provided. The storage device includes: a first memory configured to store a plurality of pieces of debug information; and a controller configured to: check an access level of target debug information among the plurality of pieces of debug information according to a debug information read command provided by a host device; and perform a security operation for the target debug information based on the access level of the target debug information.

A processing method executed by a processor included in a first communication device, the method includes outputting, from a first communication interface of the first communication device, a plurality of data items to a communication path between the first communication interface and a second communication interface of the second communication device while changing a communication setting value regarding the first communication interface; acquiring error information related to the outputting; storing the acquired error information as error management information acquired by associating the communication setting value with the error information; specifying a predetermined number of continuous communication setting values at which an error is not detected based on the error management information; setting a target setting value of the specified communication setting values for the first communication interface; and executing a communication process between the first communication interface for which the target setting value is set and the second communication interface.

Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets in compliance with an IO protocol, and a packet aligning and checking unit to align test packets generated by the packet generator with returned test packets and to compare the generated test packets with the returned data packets.

An S.M.A.R.T. threshold optimization method used for disk failure detection includes the steps of: analyzing S.M.A.R.T. attributes based on correlation between S.M.A.R.T. attribute information about plural failed and non-failed disks and failure information and sieving out weakly correlated attributes and/or strongly correlated attributes; and setting threshold intervals, multivariate thresholds and/or native thresholds corresponding to the S.M.A.R.T. attributes based on distribution patterns of the strongly or weakly correlated attributes. As compared to reactive fault tolerance, the disclosed method has no negative effects on reading and writing performance of disks and performance of storage systems as a whole. As compared to the known methods that use native disk S.M.A.R.T. thresholds, the disclosed method significantly improves disk failure detection rate with a low false alarm rate. As compared to disk failure forecast based on machine learning algorithm, the disclosed method has good interpretability and allows easy adjustment of its forecast performance.

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.