A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

A system for debugging server startups incorporated in a method applied in a server includes voltage regulators, a complex programmable logic device (CPLD), a transmitting device, and a display device. The voltage regulators transmit power-on signals required when the server is started. The CPLD receives the power-on signals, collects a second signal from the power on signals, and converts the second signals into a second data. The transmitting device receives the second data and parses the second data into a third data. The displaying device receives the third data and displays power-on signals that do not meet required standard during startup of server, according to the third data.

The present invention provides a technology for comprehensive verification of the safety of the design of functions, on the basis of a safety analysis result. The disclosed vehicle control system verification device is equipped with a storage device that stores programs for verifying the safety of the logical architecture of a vehicle control system, and a processor that reads the programs from the storage device and verifies the safety of the logical architecture. On the basis of safety analysis result information that is supplied, the processor executes a process for verifying whether the logical architecture has logical functions corresponding to the safety analysis result.

The present invention provides a technology for comprehensive verification of the safety of the design of functions, on the basis of a safety analysis result. The disclosed vehicle control system verification device is equipped with a storage device that stores programs for verifying the safety of the logical architecture of a vehicle control system, and a processor that reads the programs from the storage device and verifies the safety of the logical architecture. On the basis of safety analysis result information that is supplied, the processor executes a process for verifying whether the logical architecture has logical functions corresponding to the safety analysis result.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.