A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.

The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.

An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system.

Techniques are disclosed herein that relate to performing and managing validation tests for XR applications to provide validation for the quality and usability of the applications within XR capable user devices. An example provides a testing system that receives a request to perform validation tests for an XR application executing on an XR capable device, the request including unique testing specifications corresponding to the XR capable device. The testing system may identify testing device capabilities to perform the validation tests and select a testing device of a plurality of testing devices based at least on the testing device capabilities associated with the testing device to execute the validation tests for the XR application according to the testing specifications and report test results from the validation tests to a testing log.

Techniques are disclosed herein that relate to performing and managing validation tests for XR applications to provide validation for the quality and usability of the applications within XR capable user devices. An example provides a testing system that receives a request to perform validation tests for an XR application executing on an XR capable device, the request including unique testing specifications corresponding to the XR capable device. The testing system may identify testing device capabilities to perform the validation tests and select a testing device of a plurality of testing devices based at least on the testing device capabilities associated with the testing device to execute the validation tests for the XR application according to the testing specifications and report test results from the validation tests to a testing log.

A method for operating a control unit of a motor vehicle. A status inquiry is transmitted by a watchdog unit to a first monitoring unit, which is implemented on a first processor core of a multicore processor. A status response is ascertained by the first monitoring unit as a function of the status inquiry. A fault is ascertained by the watchdog unit as a function of the status response.

A method for operating a control unit of a motor vehicle. A status inquiry is transmitted by a watchdog unit to a first monitoring unit, which is implemented on a first processor core of a multicore processor. A status response is ascertained by the first monitoring unit as a function of the status inquiry. A fault is ascertained by the watchdog unit as a function of the status response.

A method and apparatus may include receiving a signal from a motor. The signal is received while the motor is operating. The method also includes performing a pre-processing of the signal. The method also includes inputting the signal to a 1D convolutional neural network. The method also includes detecting a fault of the motor based on the output of the neural network.