Physical or off-chip interfaces may be selectively bypassed in a boundary scan chain. A bypass control signal may be produced that indicates whether to bypass a selected one of the interfaces. In response to a first state of a bypass control signal, a multiplexer may couple the scan chain output of an interface boundary scan cell to the scan chain input of a successor boundary scan cell of the interface boundary scan cell. In response to a second state of the bypass control signal, the multiplexer may couple the scan chain output of a predecessor boundary scan cell of the interface boundary scan cell to the scan chain input of the successor boundary scan cell, bypassing the interface boundary scan cell.

Physical or off-chip interfaces may be selectively bypassed in a boundary scan chain. A bypass control signal may be produced that indicates whether to bypass a selected one of the interfaces. In response to a first state of a bypass control signal, a multiplexer may couple the scan chain output of an interface boundary scan cell to the scan chain input of a successor boundary scan cell of the interface boundary scan cell. In response to a second state of the bypass control signal, the multiplexer may couple the scan chain output of a predecessor boundary scan cell of the interface boundary scan cell to the scan chain input of the successor boundary scan cell, bypassing the interface boundary scan cell.

Temporary fault injection to existing hardware is performed using only software without changing an implementation of the hardware. A fault injection interrupt process starts on an operation of a CPU using an interrupt that is not used by software, and an internal state of hardware is updated to the same value as a result obtained when a fault has occurred during the interrupt process. A clock of the CPU during the interrupt process is accelerated so that a period of time of the interrupt process is smaller than a period of time until a fault becomes effective.

Temporary fault injection to existing hardware is performed using only software without changing an implementation of the hardware. A fault injection interrupt process starts on an operation of a CPU using an interrupt that is not used by software, and an internal state of hardware is updated to the same value as a result obtained when a fault has occurred during the interrupt process. A clock of the CPU during the interrupt process is accelerated so that a period of time of the interrupt process is smaller than a period of time until a fault becomes effective.

The invention relates to a method for the reliable transport of alarm messages in a distributed computer system, said computer system comprising components, in particular a plurality of components, the components being node computers, distributor units, sensors—preferably intelligent sensors—and actuators—preferably intelligent actuators—and all components having access to a global time of known precision, and the node computers, intelligent sensors and intelligent actuators exchanging messages via the distributor units. It is provided that the computer system includes intelligent alarm sensors or intelligent alarm sensors are assigned to the computer system, and an intelligent alarm sensor transmits two types of time-triggered messages, alarm messages having an alarm transport period prescribed a priori, and error detection messages having an error detection period prescribed a priori, and the time stamps for the occurrence of alarm events are included in an alarm monitoring interval, the alarm monitoring interval ending directly before the transmission of the alarm message and being at least twice as long as the alarm transport period, and an alarm message only being transmitted if at least one time stamp of an alarm event is included in the alarm message, and the current states of all alarms that are active immediately before the transmission of the error detection message are included in the periodic error detection messages.

A method or testing a system. Input parameters of the system are divided into a first group and a second group. Using a first method, a first selection is made from among the input parameter assignments of the first group. Using a second method, a second selection is made from among the input parameter assignments of the second group. A characteristic value is calculated from the second selection. The first selection is adapted depending on the characteristic value.

A binary patch system for a vehicle may include a memory and a controller in communication with the memory and programmed to receive original source code, identify vulnerabilities in original source code, generate binary patch based on the identified vulnerabilities, insert binary patch into original source code, receive feedback of the inserted binary patch, and update the binary patch based on the feedback.

A binary patch system for a vehicle may include a memory and a controller in communication with the memory and programmed to receive original source code, identify vulnerabilities in original source code, generate binary patch based on the identified vulnerabilities, insert binary patch into original source code, receive feedback of the inserted binary patch, and update the binary patch based on the feedback.

For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the second passing point, write data within the logic circuit of the tester identifying the second passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.