A computer-implemented system and method for storing data associated with an agent in a multi-dimensional environment via a memory architecture. The memory architecture is structured so that each unique position in the environment corresponds to a unique position within the memory architecture, thereby allowing the memory architecture to store features located at a particular position in the environment in a memory location specific to that location. As the agent traverses the environment, the agent compares the features at the agent's particular position to a summary of the features stored throughout the memory architecture and writes the features that correspond to the summary to the coordinates in the memory architecture that correspond to the agent's position. The system and method allows agents to learn, using a reinforcement signal, how to behave when acting in an environment that requires storing information over long time steps.

Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.

Embodiments of the present disclosure disclose a method and apparatus for calculating tensor data based on a computer, a medium, and a device. The method includes: determining, from a second tensor, a dimension different from a dimension of a first tensor based on dimensions of the first tensor and dimensions of the second tensor; updating stride in the different dimension to a predetermined value; reading a to-be-operated data block of the second tensor from a buffer module based on updated stride with the predetermined value in each dimension of the second tensor, where the to-be-operated data block is a data block for which padding processing is performed; and performing binary operation on the first tensor based on the to-be-operated data block of the second tensor. According to the present disclosure, broadcasting may be conveniently achieved without difficulty of hardware design being increased.

The memory control unit 12 causes a memory unit 13 to store input image data divided into a first block having pixel data of a predetermined number of pixels in a line direction for a plurality of lines, a second block having pixel data of a predetermined number of pixels following the first block in the line direction for a plurality of lines including a part of the lines of the first block, and a third block having pixel data of a predetermined number of pixels following in the line direction for a plurality of lines including a line different from the line included in the second block in the first block. The arithmetic processing unit 15 calculates an interpolation position that is a position before image conversion corresponding to a pixel position after image conversion, the memory control unit 12 reads the pixel data of the first to third blocks including the pixel data of the peripheral pixel of the interpolation position from the memory unit 13, and the interpolation processing unit 14 generates the pixel data of the interpolation position by the interpolation processing using the read peripheral pixel. The processing speed of the image processing can be improved.

A computing device performs initial processing of sensor data. The computing device performs obtaining sensor data, writing the sensor data to first addresses of a dynamically allocated buffer associated with the computing device, encoding the sensor data, writing the encoded sensor data to second addresses of the dynamically allocated buffer, in response to completing the writing of the encoded sensor data, indicating that the writing of the encoded sensor data has been completed, receiving, from a computing resource, a polling request to read the encoded sensor data, transmitting, to the computing resource, a status that the writing of the encoded sensor data to the second addresses has been completed, reading, to a memory of the computing resource, the encoded sensor data, receiving, from the computing resource, a second status that the encoded sensor data has been read, and removing, from the dynamically allocated buffer, the encoded sensor data.

Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

Improved technological solutions are introduced for providing a secure and effective and enhanced clustering/grouping solution that is useful, for example, in an online dating forum as well as any number of other industries. The ability to attend live events in person or remotely is coupled with presence location and automatic verification of user devices and identities. This allows secured communication between participants without having to disclose actual contact information of the participants or their device addresses. An improved algorithm that groups members/items effectively based on a variety of matching criteria, with lowered possibilities of errors and more efficient use of processing power, is now introduced.

A method for processing overhead of memory access includes: applying for a memory configured to perform value padding on at least one convolution operation in a deep learning model; determining input data of the deep learning model; performing deep learning processing on the input data by using the deep learning model; and releasing the memory after performing the deep learning processing.