Disclosed is a heap memory manager that manages an entry and a removal of data from a single allocated block of memory. The heap memory manager may receive a set of nodes from a tree-based representation of a point cloud or another image, may allocate a single block of memory for processing and/or rendering the set of nodes, may assign each node of the set of nodes to an exclusive range of addresses within the single block of memory, and may upload data of each of the set of nodes to the single block of memory in the exclusive range of addresses assigned to each node. A controller may then invoke a compute kernel with one or more compute kernel instances processing an address range that is different than the exclusive range of addresses assigned to each node of the set of nodes.

A hardware accelerator can store, in multiple memory storage areas in one or more memories on the accelerator, input data for each processing time step of multiple processing time steps for processing sequential inputs to a machine learning model. For each processing time step, the following is performed. The accelerator can access a current value of a counter stored in a register within the accelerator to identify the processing time step. The accelerator can determine, based on the current value of the counter, one or more memory storage areas that store the input data for the processing time step. The accelerator can facilitate access of the input data for the processing time step from the one or more memory storage areas to at least one processor coupled to the one or more memory storage areas. The accelerator can increment the current value of the counter stored in the register.

An access control method for a shared memory includes: creating and initializing the shared memory, the shared memory initialized including a plurality of region configuration objects, a plurality of block configuration objects and a plurality of data buffers; determining at least one target block according to a volume of data to be written corresponding to a first process; and writing the data by the first process into a target data buffer corresponding to the at least one target block, storing configuration information of the at least one target block to a region configuration object corresponding to a target region, and storing configuration information of the target data buffer to a block configuration object corresponding to the at least one target block.

A method includes receiving, at a controller of a computational storage (CS) device, a request to allocate computational storage to an application of a host device. The request includes a resource set ID associated with the application. The method further includes identifying a memory range within a memory region of the CS device. The method further includes storing, in a data structure associated with the resource set ID, an association between a memory range identifier (ID) of the memory range, the memory region, and an offset within the memory region. The method further includes sending the memory range ID to the host device.

A direct memory access (DMA) controller comprises template storage circuitry to store at least one DMA template indicative of a DMA data access pattern. Each DMA template comprises enable indications settable to an enable state or a disable state. In response to a DMA command associated with a source address, a destination address, a source DMA template, and a destination DMA template, DMA control circuitry generates a set of DMA memory access requests to copy data from source memory system locations to destination memory system locations. The source/destination memory system locations are selected to have addresses which are offset relative to the source/destination address by offset amounts corresponding to positions of enable indications set to the enable state within the source/destination DMA template. The source/destination DMA templates allow irregular patterns of DMA accesses to be controlled in fewer DMA commands.

A memory access command to be performed on a die of a memory device is received, wherein the memory access command comprises a base partition number and a base page address. The memory access command is converted into a plurality of commands based on a number of partitions associated with the die. A respective partition number derived from the base partition number is determined for each command of the plurality of commands. A respective page address associated with each command of the plurality of commands is determined using the base page address. The plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.

Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

A method includes transferring data out of a first buffer coupled to a first plane of a plurality of planes of a memory component, where the data was previously transferred from the first plane to the first buffer responsive to an access request to sense data stored in the plurality of planes of the memory component. The method further includes transferring, subsequent to transferring the data out of the first buffer and independently of a command from a processing device, data out of a second buffer coupled to a second plane of the plurality of planes of the memory component, where the data transferred out of the second buffer was previously transferred from the second plane to the second buffer responsive to the access request.

A method begins by a processing module of a storage network analyzing storage network memory for a level of usability and based on the analyzing, selecting alternative memory available for receipt of encoded data slices stored in current memory, where a data object is segmented into a plurality of data segments and a data segment of the plurality of data segments is dispersed error encoded in accordance with dispersed error encoding parameters to produce a set of encoded data slices. The method continues with the processing module determining whether to move encoded data slices from current memory to alternative memory and based on a determination to move slices, allocating alternative memory. Finally, the processing module moves at least some encoded data slices from a current memory to alternate memory and updates a memory assignment mechanism for the at least some encoded data slices.

Disclosed herein are system, method, and computer program product embodiments for storing an object onto a first or second page. An embodiment operates by receiving the object and determining that the first page has sufficient unused space for storing at least one byte of the object. Thereafter, a data block of the object is created to comprise at least one byte of the object. The data block is then stored on the first page or the second page, and a location of the object's first data block is recorded. Thereafter, a pointer corresponding to the location of the object's first data block for loading the object is provided.