Disclosed are an electronic device and a control method thereof. The electronic device according to the present disclosure includes a memory, a cache memory, a CPU, and includes a processor which controls the electronic device by using a program stored in the memory, wherein the CPU monitors an input address through which an input value is accessed in the cache memory, and changes the input address when the input address through which the input value is accessed in the cache memory is changed to a preset pattern.

A method for managing memory for applications in a computing system includes receiving a selection of a preferred application. During user-controlled operation over the application, the transitions of selected application between foreground and background are monitored. A retention of the application in memory is triggered upon a transition of the application to background during the user operation. Retention of the application includes compressing memory portions of the application. Accordingly, the application is retained within the memory based on said compressed memory portions. A requirement to restore the retained application is sensed based on either a user selection or an automatically generated prediction and the application is restored from the retained state back to the foreground.

An infrastructure for mapping between logic block addresses (LBAs) and physical block addresses (PBAs). A disclosed method includes: receiving a request the specifies an LBA; determining an applicable zone based on the LBA from a set of zones, wherein the set of zones expose an LBA address space of the storage device; identifying at least one tree from a set of trees having a root node associated with the applicable zone; traversing the at least one tree to identify a set of leaf nodes based on the LBA, wherein each leaf node points to an mpage; and determining corresponding PBA information for the LBA by examining mapping information contained in each mpage.

The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module. The memory controller comprises a central buffer coupled between the memory module and the host controller via a command/address channel, wherein the central buffer is configured to receive a command/address signal from the host controller and provide the command/address signal to the memory module. The central buffer comprises: a recognition block coupled to the command/address channel to receive the command/address signal, wherein the recognition block is configured to generate access history information based on the received command/address signal; a compression block coupled to the recognition block to receive the access history information, wherein the compression block is configured to compress the access history information; and a transmission block, wherein the compressed access history information is transmitted out from the central buffer via the transmission block.

A server system generates a model of a first memory architecture of a client device, the model of the first memory architecture including a GPU memory portion and a CPU memory portion. The server system receives a representation of a first image asset, and stores a first texture image corresponding to the first image asset in the GPU memory portion of the model at the server system. The first texture image is stored in the GPU memory portion of the client device. The server system determines, using the model, that the GPU memory portion at the client device needs to be reallocated. The server system identifies, using the model, one or more texture images that are stored in the GPU memory portion at the client device to evict and transmits an instruction, to the client device, to evict the one or more texture images from the GPU memory portion.

A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.

A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.