The system can receive data to be written to a non-volatile memory in the distributed storage system. The received data can include a plurality of input segments. The system can assign consecutive logical block addresses (LBAs) to the plurality of input segments. The system can then compress the plurality of input segments to generate a plurality of fixed-length compressed segments, with each fixed-length compressed segment aligned with a physical block address (PBA) in a set of PBAs. The system compresses the plurality of input segments to enable an efficient use of storage capacity in the non-volatile memory. Next, the system can write the plurality of fixed-length compressed segments to a corresponding set of PBAs in the non-volatile memory. The system can then create, in a data structure, a set of entries which map the LBAs of the input segments to the set of PBAs. This data structure can be used later by the system when processing a read request including a LBA.

A method of storing data is provided. The method includes receiving a plurality of data blocks provided to a hyperscaler system. The method also includes determining a corresponding property for each data block of the plurality of data blocks. The method further includes identifying a set of data blocks from the plurality of data blocks. Each data block of the set of data blocks is associated with a first property. The method further includes storing the set of data blocks in a first zone of a zoned storage system, based on the first property.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Systems, apparatuses, and methods related log compression are described. In an example, a system log that identifies targeted data may be compiled in a memory resource during an execution of an operation using that memory resource. The system log may be analyzed utilizing a portion of the memory resource that would otherwise be available to be utilized in the execution of the operation. The system log may be compressed during the execution of the operation, the level or timing of such compression may be based on the analysis that occurs contemporaneous to or as a result of executing the operation. In some examples, compressing the system log may include discarding a portion of the system log. Compressing the system log may also include extracting the targeted data from the system log as the system log is being compiled and converting the extracted targeted data to structured data.

Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.