An illustrative method includes a data protection system performing, for a storage system, a first security threat detection process, determining, based on the performing of the first security threat detection process, that the storage system is possibly being targeted by a security threat, and performing a second security threat detection process, the second security threat detection process providing higher confidence threat detection than the first security threat detection process.

A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.

A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.

The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.

For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

The technology of this application relates to a data index management method and apparatus in a storage system, and relates to the field of computer technologies, to help create a data index by using a data index operation unit with a proper grain, thereby reducing storage space occupied by data indexes. The method includes obtaining first to-be-written data, where a logical address range of the first to-be-written data is a first logical address range, and generating a data index based on an alignment status between a logical address range of a to-be-generated data index in the first logical address range and data index operation units with different lengths in the storage system, where the storage system includes a data index operation unit with a first length and a data index operation unit with a second length, and the first length is greater than the second length.

The technology of this application relates to a data index management method and apparatus in a storage system, and relates to the field of computer technologies, to help create a data index by using a data index operation unit with a proper grain, thereby reducing storage space occupied by data indexes. The method includes obtaining first to-be-written data, where a logical address range of the first to-be-written data is a first logical address range, and generating a data index based on an alignment status between a logical address range of a to-be-generated data index in the first logical address range and data index operation units with different lengths in the storage system, where the storage system includes a data index operation unit with a first length and a data index operation unit with a second length, and the first length is greater than the second length.

Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.

Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.