Systems, methods, and apparatuses for implementing non-redundant metadata storage addressed by bounded capabilities are described. In certain examples, a hardware processor core comprises an execution circuit to generate a first memory access request for a first single object in memory by a first capability and a second memory access request for a second different sized single object in the memory by a second capability, wherein a format of each of the first capability and the second capability comprises a single metadata field for access control of a single object in the memory, a bounds field that is to indicate a lower bound and an upper bound of the single object in the memory to which the single metadata field authorizes access, and an address field to indicate an address in the single object that is to be accessed; and a capability management circuit to determine a first location of a corresponding first metadata field in the memory based on the bounds field of the first capability, proceed with the first memory access request in response to a match of metadata in the single metadata field of the first capability against metadata at the corresponding first metadata field in the memory, determine a second location of a corresponding second metadata field in the memory based on the bounds field of the second capability, and proceed with the second memory access request in response to a match of metadata in the single metadata field of the second capability against metadata at the corresponding second metadata field in the memory.

A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.

To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller transmits a specified logical address range, an update frequency level of the specified logical address range, and specified data to a device controller. On the basis of the update frequency level of the specified logical address range, the device controller determines whether the specified data is compressed or not. When determination is made that the specified data is compressed, the device controller compresses the specified data to generate compressed data, and writes the compressed data into a non-volatile memory. When determination is made that the specified data is not compressed, the device controller writes the specified data into the non-volatile memory.

Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.

A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the electronic apparatus and includes following steps. Region descriptor entries are fetched from a region descriptor table. Each of the region descriptor entries includes a block initial address and a block length to describe a memory block of a memory module. According to the block initial addresses and the block lengths of the region descriptor entries, a portion of the region descriptor entries are adjusted to be at least one current region descriptor entry. Based on the at least one current region descriptor entry, a current region descriptor table is generated.

A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the electronic apparatus and includes following steps. Region descriptor entries are fetched from a region descriptor table. Each of the region descriptor entries includes a block initial address and a block length to describe a memory block of a memory module. According to the block initial addresses and the block lengths of the region descriptor entries, a portion of the region descriptor entries are adjusted to be at least one current region descriptor entry. Based on the at least one current region descriptor entry, a current region descriptor table is generated.

Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.

Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.

Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.