G06F12/06

High capacity memory system using standard controller component
11568919 · 2023-01-31 · ·

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

High capacity memory system using standard controller component
11568919 · 2023-01-31 · ·

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

ENHANCEMENTS TO DATAGEN ALGORITHM TO GAIN ADDITIONAL PERFORMANCE FOR L1 DATASET
20230236965 · 2023-07-27 ·

One example method, which may be performed in a dedupe environment, includes receiving a data call from a caller, in response to the data call, generating data that fulfills a portion of the data call, storing the data in a buffer, checking an offset to determine if the offset maps to the buffer, and when the offset maps to the buffer, altering the data that is located at the offset in the buffer. When the offset does not map to the buffer, the generation of data may cease.

ENHANCEMENTS TO DATAGEN ALGORITHM TO GAIN ADDITIONAL PERFORMANCE FOR L1 DATASET
20230236965 · 2023-07-27 ·

One example method, which may be performed in a dedupe environment, includes receiving a data call from a caller, in response to the data call, generating data that fulfills a portion of the data call, storing the data in a buffer, checking an offset to determine if the offset maps to the buffer, and when the offset maps to the buffer, altering the data that is located at the offset in the buffer. When the offset does not map to the buffer, the generation of data may cease.

INTELLIGENT DEFRAGMENTATION IN A STORAGE SYSTEM
20230236966 · 2023-07-27 ·

Techniques are provided for implementing intelligent defragmentation in a storage system. A storage control system manages a logical address space of a storage volume. The logical address space is partitioned into a plurality of extents, wherein each extent comprises a contiguous block of logical addresses of the logical address space. The storage control system monitors input/output (I/O) operations for logical addresses associated with the extents, and estimates fragmentation levels of the extents based on metadata associated with the monitored I/O operations. The storage control system identifies one or more extents as candidates for defragmentation based at least on the estimated fragmentation levels of the extents.

Firmware loading for a memory controller
11714757 · 2023-08-01 · ·

Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Methods and apparatus for persistent data structures

A method may include storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A system may include a processor, a volatile memory coupled to the processor, and a persistent memory coupled to the processor. The processor may be configured to execute procedures including storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A method may include storing at least a portion of a transient part of a persistent data structure in volatile memory, and storing at least a portion of a persistent part of the persistent data structure in persistent memory.

APPARATUS AND METHOD TO SHARE HOST SYSTEM RAM WITH MASS STORAGE MEMORY RAM

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

DATA DEDUPLICATION LATENCY REDUCTION

Aspects of the present disclosure relate to reducing the latency of data deduplication. In embodiments, an input/output (IO) workload received by a storage array is monitored. Further, at least one IO write operation in the IO workload is identified. A space-efficient probabilistic data structure is used to determine if a director board is associated with the IO write. Additionally, the IO write operation is processed based on the determination.

PROCESSING WORK ITEMS IN PROCESSING LOGIC
20230229592 · 2023-07-20 ·

A plurality of work items are processed through a processing pipeline comprising a plurality of stages in processing logic. The processing of a work item includes: (i) reading data in accordance with a memory address associated with the work item, (ii) updating the read data, and (iii) writing the updated data in accordance with the memory address associated with the work item. The method includes processing a first work item and a second work item through the processing pipeline, wherein the processing of the first work item through the pipeline is initiated earlier than the processing of the second work item, and where it is determined that the first and second work items are associated with the same memory address, first updated data of the first work item is written to a register in the processing logic, and the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory.